A resource-reusing FPGA architecture for GARI-structured message-passing decoding of quantum LDPC codes with correlated errors achieves 596 ns average latency and 6x lower resource use than prior GARI hardware on a VCU19P device.
Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes,
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A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI
A resource-reusing FPGA architecture for GARI-structured message-passing decoding of quantum LDPC codes with correlated errors achieves 596 ns average latency and 6x lower resource use than prior GARI hardware on a VCU19P device.