Combining short-distance spatial elimination with stratified or k-means sampling lowers Gaussian-process prediction error on wafer and FPGA test data by roughly 8% to 16%.
Advanced test strategies for semi- conductor wafer inspection using machine learning,
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Optimizing FPGA and Wafer Test Coverage with Spatial Sampling and Machine Learning
Combining short-distance spatial elimination with stratified or k-means sampling lowers Gaussian-process prediction error on wafer and FPGA test data by roughly 8% to 16%.