Optimizing FPGA and Wafer Test Coverage with Spatial Sampling and Machine Learning

Riaz-ul-haque Mian; Wang WeiQuan

REVIEW 3 major objections 5 minor 21 references

Optimizing FPGA and Wafer Test Coverage with Spatial Sampling and Machine Learning

T0 review · 3 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read Adding a spatial minimum-distance rule to stratified and k-means sampling improves Gaussian process predictions of untested wafer and FPGA devices, cutting RMSD by 8.84–16.49%.

desk verdict Sensible spatial-sampling idea, but the 13–16% improvement claims rest on single unreplicated runs and an apparently leaked tuning file. read the letter →

arxiv 2506.03556 v1 pith:DC5JK54X submitted 2025-06-04 cs.LG

Wang WeiQuan , Riaz-ul-Haque Mian This is my paper

classification cs.LG

keywords wafertestingFPGAGaussianprocessregressionshortdistanceeliminationspatialsamplingk-meansclusteringstratifiedsemiconductortestcost

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper is trying to establish that the spatial layout of the small set of physically tested semiconductor devices matters even when the sample is already chosen to cover the range of measured values. Its proposal, Short Distance Elimination (SDE), is a geometric filter: as candidate training points are drawn, any point that lies within a threshold distance in x or y of an already selected point is rejected, forcing the 10% training set to spread across the wafer or FPGA. Hybridized with stratified sampling (S-SDE) and k-means clustering (K-SDE), this filter is reported to reduce Gaussian process regression root-mean-square deviation by 16.49% and 16.26% on wafer data and by 8.84% and 13.07% on FPGA data relative to the respective baselines. A sympathetic reader should care because, if correct, the result would show that test-cost savings can be obtained by a simple geometric constraint rather than by more expensive active-learning or optimization schemes.

What carries the argument

The load-bearing object is the Short Distance Elimination (SDE) algorithm, a thresholded spatial filter defined by Δ=1 when |x_i−x_j|≥α and |y_i−y_j|≥β for every previously selected point; candidates failing this test are discarded and, if too few points survive, the training set is topped up from the discarded candidates. In the hybrid methods, SDE runs inside each k-means cluster or each stratified value bin, so the final 10% is representative in measurement space and spread in physical space. The predictor that turns sampling choices into a score is Gaussian Process Regression with the RBF kernel, and the score is the RMSD on the 90% held-out points.

What would settle it

Repeat each of the five sampling methods many times with different random seeds on the same 23 wafers and 10 FPGAs, and compare the distributions of RMSD; if the average advantage of K-SDE over k-means or S-SDE over stratified is smaller than the spread of repeated runs, the claimed improvements would not be distinguishable from sampling noise.

Watch

Extended reading notes

Core claim

The paper's central claim is that K-SDE and S-SDE deliver the lowest prediction error among the five compared samplers because SDE fills a gap left by value-only partitioning: stratified and k-means sampling balance the training set across measurement values but ignore physical coordinates, so they can leave spatially clustered points that carry redundant information. With the RBF kernel and hyperparameters fit by maximum likelihood, the reported average RMSD values are 0.035 for K-SDE versus 0.041 for k-means on wafer data and 0.709 versus 0.815 on FPGA data, and 0.042 for S-SDE versus 0.050 for stratified on wafer data and 0.898 versus 0.985 on FPGA data. The authors choose (α,β)=(2,2) as the distance thresholds because a sweep over {0,1,2,3,4}² on one wafer file gave its lowest RMSD, 0.0292. On the paper's own terms, the discovery is that spatial dispersion itself is a source of predictive accuracy in GPR-based partial testing.

Load-bearing premise

The paper treats a single RMSD value per file, computed without repeated random draws or significance tests, as a stable measure of each sampling method's performance, so the reported percentage improvements assume this single draw is representative rather than lucky.

Editorial extensions

If this is right

K-SDE, the best overall method in the paper, lowers average RMSD by 16.26% over k-means on wafer data and by 13.07% on FPGA data.
S-SDE lowers average RMSD by 16.49% over stratified sampling on wafer data and by 8.84% on FPGA data.
Measurement-value-aware samplers (stratified and k-means) beat random sampling on both datasets, supporting the paper's claim that value coverage helps GPR predictions.
The advantage of SDE-based methods appears consistently across individual wafers, with per-wafer improvements between 7.89% and 28.91%, and across nearly all 32 FPGA paths, not only in the averages.
The chosen threshold (α,β)=(2,2), fixed from one parameter sweep, is treated as a universal setting for all subsequent wafer and FPGA experiments.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

An implication the authors leave implicit is that, because SDE is a purely geometric preprocessing step independent of the predictor, the same filter should transfer to other regression models and other spatial datasets, though the benefit would probably shrink whenever the true spatial field varies on scales smaller than the enforced separation.
A plausible mechanism, not stated in the paper, is that SDE removes training pairs closer than the RBF kernel's length scale, and those pairs contribute little new information; this would make SDE a crude substitute for optimized experimental design in GPR.
A direct test would be to compare K-SDE and S-SDE against explicit space-filling designs, such as farthest-point sampling or Latin hypercubes, on the same wafer and FPGA files, because the reported gains are relative to k-means and stratified sampling rather than to all possible spatial designs.
The global choice of (α,β)=(2,2) is based on a single wafer file, so an obvious extension is to set the thresholds per file or in units of the spatial correlation length; the wafer-level variation in improvement suggests the optimal spacing may vary.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

What should you know about this paper? The core idea is sensible: when training GPR on spatial test data, don't let training points bunch up. The proposed Short Distance Elimination (SDE) is a simple way to enforce a minimum spacing, and combining it with stratified or k-means sampling (S-SDE, K-SDE) is a natural extension. The problem is that the headline numbers rest on a single unreplicated run per file, with no variance or significance tests, so the claimed 13–16% gains are not yet supported.

What's genuinely new: the specific hybrid combinations and the evaluation on real industrial wafer and FPGA data. The SDE rule is a minor variant of farthest-point and other distance-based sampling methods cited in the paper, so the algorithmic novelty is modest. That's fine; not every contribution needs a new principle. The paper is honest about the GPR framework and uses real data, which is more than many simulation-only studies do.

The soft spots are serious but localized. Each sampling method is run once per file; random sampling, within-stratum/within-cluster draws, and the SDE initial point are all stochastic, so one run per file cannot distinguish the sampling rule from noise. The parameter sweep for (alpha,beta) is done on one wafer file, and that same file appears to be included in the averaged results — no hold-out is mentioned. Adding a simple repeated-measures design (e.g., 20 random seeds per file, paired tests) would answer the main criticism. The lack of data or code also limits reproducibility.

In short, the paper is a reasonable engineering idea with weak evidence. I'd tell the authors to rerun with multiple seeds, report confidence intervals, and exclude the tuning file from evaluation. The method might well work; the current evidence just doesn't show it.

For you: this is a good seed for a reading-group discussion on empirical rigor in ML papers. I'd give it a serious referee — the topic is real and the fix is straightforward — but I would not cite the numeric gains until they're properly validated.

Referee Report

3 major / 5 minor

Summary. The paper addresses semiconductor test-cost reduction by selecting 10% of measured wafer or FPGA data to train a Gaussian Process Regression (GPR) model and predict the remaining 90%. It compares random, stratified, and k-means sampling against two proposed hybrids, S-SDE and K-SDE, which apply a Short Distance Elimination (SDE) step to enforce spatial dispersion within each stratum or cluster. A parameter sweep over thresholds (alpha, beta) selects (2,2), and the paper reports that K-SDE improves over k-means by 16.26% (wafer) and 13.07% (FPGA), while S-SDE improves over stratified sampling by 16.49% (wafer) and 8.84% (FPGA). The evaluation uses real industrial wafer data and Xilinx Artix-7 FPGA ring-oscillator measurements.

Significance. If the reported improvements hold, the work offers a simple, low-cost modification to existing sampling strategies with practical value for semiconductor test reduction. The paper's strengths include the use of real production wafer data and actual silicon FPGA measurements, a clear algorithmic description of SDE, and per-wafer and per-path breakdowns of the comparisons. However, the headline percentages rest on single unreplicated runs of stochastic samplers, with no error bars, confidence intervals, or significance tests, so the central empirical claim is not yet established. The parameter tuning on one wafer file without an explicit hold-out also introduces potential selection bias. The idea is plausible and worth further validation, but the current evidence is insufficient for the strength of the conclusions.

major comments (3)

[Section V-D / Table II] The reported RMSD values are the outcome of one unreplicated run per wafer or FPGA file, yet every sampling method is stochastic: random sampling in Eq. (5), within-stratum draws in Eq. (8), within-cluster draws in Eq. (11), and the initial point and candidate order in SDE (Section IV-A). One run per file cannot separate the effect of the sampling rule from run-to-run seed variability. For example, the wafer k-means-to-K-SDE difference of 0.006 (0.041 vs. 0.035) is small relative to plausible variation at a 10% training fraction. Please repeat each method many times, report paired differences with confidence intervals or significance tests, and base the headline 13-16% improvements on those distributions rather than on single-point averages.
[Section IV-B / Section V-F / Table I] The optimal (alpha, beta) = (2,2) is selected by minimizing RMSD on one 'randomly selected wafer file,' and then 'all subsequent experiments adopt this parameter configuration.' The paper never states whether that tuning file was excluded from the averaged results in Table II. If it was included, the reported improvements are optimistically biased; if it was excluded, the exclusion must be stated. In either case, a single-file sweep with no validation or sensitivity analysis does not establish that (2,2) generalizes across all wafers and FPGAs. A cross-validation or held-out tuning-file protocol is needed to support the claim that the method consistently outperforms the baselines.
[Eq. (12) and Section IV-A] The distance function accepts a candidate only when both |x_i - x_j| >= alpha and |y_i - y_j| >= beta, so a point that is spatially far in one coordinate but close in the other is rejected. This is a stronger restriction than 'excludes spatially proximate points.' The paper should state this explicitly and justify why an AND condition is appropriate; a sensitivity analysis showing how the selected sample size and prediction error change under an OR condition or a Euclidean-distance condition would clarify whether the reported gains are due to the spatial dispersion mechanism or to the specific threshold geometry.

minor comments (5)

[Section V-D] The heading 'D. Results and Discussion' is followed immediately by the next subsection with no actual results or discussion text under D; please fill this section or renumber the subsections.
[Figure 2] The pseudocode in Figure 2 contains inconsistent variable names such as 'Select=Selected row' and 'Drop=Selected row', which makes the algorithm difficult to reproduce; please align the notation with the text and equations.
[Section V-A] The paper states that 16 sites are 'treated as a single entity,' but does not report whether the site structure affects the spatial covariance or the sampling behavior; a brief comment on this would help the reader judge the spatial-coordinate interpretation.
[Reference [1]] Reference [1] is cited in the abstract and in Section II-C but is not clearly introduced in relation to the proposed SDE method; please clarify how the present work differs from or extends the farthest-point sampling approach of Zhang and Liu.
[Table I] The table title says 'SDE RMSD (for one wafer data file)' while the text in Section IV-B says the sweep was performed on a 'randomly selected wafer file'; please state which wafer file was used and why it was selected.

Circularity Check

1 steps flagged · score 3.0 of 10

Empirical comparisons are largely out-of-sample, but the (α,β)=(2,2) setting is tuned on a wafer file inside the same evaluation lot with no documented exclusion; self-citations are background only.

fitted input called prediction [Abstract; Section IV-B 'Parameter Sweep and Optimal (α, β)'; Section V-F; Table I; Section V-G/Table II]
"A parameter sweep was conducted over the (α, β) thresholds—where α, β ∈ {0,1,2,3,4} and not both zero—to identify the optimal combination that minimizes RMSD. Experimental results on a randomly selected wafer file reveal that (α, β) = (2,2) yields the lowest RMSD. Accordingly, all subsequent experiments adopt this parameter configuration."

(α,β) is fit by minimizing RMSD on one wafer file from the same 23-wafer lot, and the headline wafer improvements (K-SDE vs k-means 16.26%, S-SDE vs stratified 16.49%) are averages over that lot (Section V-B step 5: 'the average RMSD for wafer and FPGA datasets is computed') with no statement that the tuning file was excluded. The wafer result therefore mixes in-sample selection with out-of-sample prediction, and the fitted configuration is presented as the fixed setting for the whole evaluation. The circularity is partial, not by construction: Table I shows SDE RMSD is nearly flat (0.0292–0.0309) across all 24 configurations, so the specific (2,2) choice does not manufacture the k-means/stratified gap, and the FPGA claims (13.07%, 8.84%) are entirely out-of-sample for this hyperparameter.

full rationale

This is an empirical benchmark study rather than a derivational chain, so most circularity patterns do not apply. Each component is independently defined: GPR with a standard RBF kernel (Eqs. 1–3), the sampling strategies (Eqs. 5–11), SDE (Eq. 12), the hybrids (Eqs. 13–18), and RMSD (Eq. 19). No quantity is defined in terms of a claimed outcome, so there is no self-definitional step. The authors' self-citations, [7] and [12], support only background statements that GPR with spatial kernels suits semiconductor data; that premise is independently backed by external sources [2], [8], [9] and is not the paper's load-bearing claim. The only fitting-into-evaluation issue is the (α,β) sweep: it is run on one wafer file from the same 23-wafer lot, and the wafer averages in Table II and Fig. 7 include that lot with no documented exclusion, so the reported wafer improvements are partially in-sample. This reduction is partial rather than forced because Table I is nearly flat across all parameter combinations and the FPGA results are wholly out-of-sample. The 'novel algorithm' framing is overstated since SDE is attributed to the external farthest-point-sampling work [1], but that is a contribution-accuracy concern, not circularity. The single-run protocol with no error bars or significance tests (Section V-D, which is also an empty section header) is a statistical robustness limitation and is not treated here as circularity. Net assessment: the central claim retains independent empirical content on out-of-sample wafer and FPGA files, with a moderate tuning-overlap caveat warranting score 3.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The paper introduces no new physical entities. Its central load-bearing additions are the alpha and beta thresholds selected on one wafer and the fixed k-means cluster count, plus the untested assumptions that GPR with an RBF kernel is appropriate and that the spatial field remains smooth after preprocessing.

free parameters (4)

alpha (SDE X-distance threshold) = 2
X-axis distance threshold in SDE; selected by RMSD sweep over {0..4} on one wafer file (Section IV-B) and fixed for all experiments.
beta (SDE Y-distance threshold) = 2
Y-axis distance threshold in SDE; selected jointly with alpha by the same RMSD sweep.
k (number of k-means clusters) = 7
Fixed without justification in Section III-B3; affects the k-means and K-SDE baselines.
GPR hyperparameters (length scale, signal variance, noise variance) = MLE per dataset
Estimated by maximum likelihood for each training set (Section V-B3); values are not disclosed.

assumptions (5)

standard math Gaussian process joint Gaussian assumption
Equation (1) in Section III-A1; standard GP theory from Rasmussen and Williams [2].
domain assumption RBF kernel is an appropriate covariance model for wafer and FPGA spatial measurements
Equation (2), Section III-A2; the paper asserts this modeling choice without testing alternatives.
domain assumption Measurement fields are smooth enough in space that GPR can extrapolate from 10% spatially spread samples
Section II-A and V-E; if the fields are not spatially smooth, the spatial sampling strategy loses its rationale.
domain assumption Removing faulty dies and merging 16 sites does not distort the spatial field
Section V-A1; preprocessing choices are stated but their effect on the results is not analyzed.
ad hoc to paper Thresholds (alpha, beta) = (2, 2) selected on one wafer generalize to all wafers and FPGAs
Section IV-B and V-F; this is a tuning-to-data choice without independent validation.

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Cite this review

Pith. "Pith review of Optimizing FPGA and Wafer Test Coverage with Spatial Sampling and Machine Learning." pith.science (2026). https://pith.science/paper/DC5JK54X

@misc{pith2026250603556,
  author       = {Pith},
  title        = {Pith review of: Optimizing FPGA and Wafer Test Coverage with Spatial Sampling and Machine Learning},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DC5JK54X}},
  note         = {Machine review of arXiv:2506.03556}
}

read the original abstract

In semiconductor manufacturing, testing costs remain significantly high, especially during wafer and FPGA testing. To reduce the number of required tests while maintaining predictive accuracy, this study investigates three baseline sampling strategies: Random Sampling, Stratified Sampling, and k-means Clustering Sampling. To further enhance these methods, this study proposes a novel algorithm that improves the sampling quality of each approach. This research is conducted using real industrial production data from wafer-level tests and silicon measurements from various FPGAs. This study introduces two hybrid strategies: Stratified with Short Distance Elimination (S-SDE) and k-means with Short Distance Elimination (K-SDE). Their performance is evaluated within the framework of Gaussian Process Regression (GPR) for predicting wafer and FPGA test data. At the core of our proposed approach is the Short Distance Elimination (SDE) algorithm, which excludes spatially proximate candidate points during sampling, thereby ensuring a more uniform distribution of training data across the physical domain. A parameter sweep was conducted over the (alpha, beta) thresholds, where alpha and beta are in the range {0, 1, 2, 3, 4} and not both zero, to identify the optimal combination that minimizes RMSD. Experimental results on a randomly selected wafer file reveal that (alpha, beta) equal (2, 2) yields the lowest RMSD. Accordingly, all subsequent experiments adopt this parameter configuration. The results demonstrate that the proposed SDE-based strategies enhance predictive accuracy: K-SDE improves upon k-means sampling by 16.26 percent (wafer) and 13.07 percent (FPGA), while S-SDE improves upon stratified sampling by 16.49 percent (wafer) and 8.84 percent (FPGA).

Figures

Figures reproduced from arXiv: 2506.03556 by the authors.

**Figure 2.** Sampling Process of the Proposed SDE Algorithm with k-means [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Heatmap illustrating the spatial distribution in Wafer. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗

Figures from the paper (3 more)

**Figure 4.** Figure 4: Heatmap illustrating the spatial distribution in FPGA. [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]

**Figure 5.** Figure 5: Comparison with Baseline Sampling Methods across FPGAs. [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]

**Figure 6.** Figure 6: Comparison with Baseline Sampling Methods Across All Paths of [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]

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Works this paper leans on

21 extracted references · 19 canonical work pages

[1]

Farthest-point sampling for wafer-level variation modeling,

Y . Zhang and X. Liu, “Farthest-point sampling for wafer-level variation modeling,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 5, pp. 900–912, 2021

work page 2021
[2]

C. E. Rasmussen and C. K. I. Williams,Gaussian Processes for Machine Learning. Cambridge, MA: MIT Press, 2006

2006
[3]

Machine learning applications in semiconductor manufacturing: A review,

S. Lee, H. Wang, and K. K. Kim, “Machine learning applications in semiconductor manufacturing: A review,”Journal of Manufacturing Systems, vol. 57, pp. 468–484, 2020

work page 2020
[4]

Optimizing test yield in semiconductor production through hybrid sampling techniques,

X. Li, Y . Zhang, and Y . Sun, “Optimizing test yield in semiconductor production through hybrid sampling techniques,”IEEE Transactions on Automation Science and Engineering, vol. 15, no. 4, pp. 1713–1723, 2018. 0 5 10 15 20 Wafer Index 0.030 0.035 0.040 0.045 0.050 0.055 0.060RMS Error Stratified vs S-SDE Stratified S-SDE 0 5 10 15 20 Wafer Index k-means...

work page 2018
[5]

Advanced test strategies for semi- conductor wafer inspection using machine learning,

T. Nguyen, S. Hu, and Y . C. Chen, “Advanced test strategies for semi- conductor wafer inspection using machine learning,”IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 3, pp. 391–400, 2019

work page 2019
[6]

Uncertainty-driven sampling for efficient wafer testing,

M. Chen and H. Mallick, “Uncertainty-driven sampling for efficient wafer testing,”IEEE Transactions on Computer-Aided Design of In- tegrated Circuits and Systems, vol. 40, no. 12, pp. 2450–2461, 2021

work page 2021
[7]

Efficient wafer-level spatial variation modeling for multi-site rf IC testing,

M. R. ul Haqueet al., “Efficient wafer-level spatial variation modeling for multi-site rf IC testing,”IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E107-A, no. 8, pp. 1139–1150, 2024

work page 2024
[8]

Wafer-level variation modeling for multi-site RF IC testing via hier- archical gaussian process,

M. Shintani, M. Inoue, T. Nakamura, M. Kajiyama, M. Eikiet al., “Wafer-level variation modeling for multi-site RF IC testing via hier- archical gaussian process,” inProceedings of the IEEE International Test Conference (ITC), 2021, pp. 103–112

work page 2021

Show all 21 references

[9]

C. M. Bishop,Pattern Recognition and Machine Learning. New York: Springer, 2006

2006
[10]

A survey of spatial sampling techniques for industrial applications,

R. Garc ´ıa, A. Fern ´andez, and R. Moliner, “A survey of spatial sampling techniques for industrial applications,”IEEE Access, vol. 7, pp. 92 892– 92 905, 2019

2019
[11]

Comparison of sampling techniques for RF test data in semiconductor manufacturing,

P. S. Roy and N. Khurana, “Comparison of sampling techniques for RF test data in semiconductor manufacturing,”Microelectronics Reliability, vol. 123–125, p. 113436, 2021

2021
[12]

Custom adaptive kernel strategies for gaussian process regression in wafer-level modeling and FPGA delay analysis,

R. U. H. Mian, F. Ahmed, Y . Hagihara, and Y . Souma, “Custom adaptive kernel strategies for gaussian process regression in wafer-level modeling and FPGA delay analysis,” Preprints, 2025, *Online*

2025
[13]

Efficient large-scale GPR via inducing-point sampling in spatial domains,

L. Zhao and Y . Tian, “Efficient large-scale GPR via inducing-point sampling in spatial domains,”Pattern Recognition, vol. 110, p. 107637, 2021

2021
[14]

A stratified sampling strategy for semiconductor quality prediction,

C.-L. Chen, C.-C. Sun, and S.-C. Hsiao, “A stratified sampling strategy for semiconductor quality prediction,”IEEE Transactions on Semicon- ductor Manufacturing, vol. 31, no. 2, pp. 278–288, 2018

2018
[15]

Spatial stratified sampling for environmental mon- itoring applied to wafer testing,

J. Park and S. J. Lee, “Spatial stratified sampling for environmental mon- itoring applied to wafer testing,”Environmental Science and Pollution Research, vol. 27, no. 14, pp. 17 300–17 310, 2020

2020
[16]

Data clustering: 50 years beyond K-means,

A. K. Jain, “Data clustering: 50 years beyond K-means,”Pattern Recognition Letters, vol. 31, no. 8, pp. 651–666, 2010

2010
[17]

Adaptive sampling strategies for FPGA testing using deep gaussian processes,

S. Kumar and M. Gupta, “Adaptive sampling strategies for FPGA testing using deep gaussian processes,”ACM Transactions on Design Automation of Electronic Systems, vol. 26, no. 3, pp. 45:1–45:27, 2021

2021
[18]

Hybrid spatial-value sampling for process monitor- ing in IC fabrication,

J. Li and T. Wang, “Hybrid spatial-value sampling for process monitor- ing in IC fabrication,”IEEE Access, vol. 9, pp. 12 000–12 012, 2021

2021
[19]

Distance-based clustering for sensor placement in wafer inspection,

A. Das and P. Roy, “Distance-based clustering for sensor placement in wafer inspection,”Sensors, vol. 20, no. 4, p. 1100, 2020

2020
[20]

Graph-based sampling in gaussian process models for semiconductor reliability prediction,

K. Singh and D. Patel, “Graph-based sampling in gaussian process models for semiconductor reliability prediction,”Reliability Engineering & System Safety, vol. 205, p. 107254, 2021

2021
[21]

Active learning for spatial sampling in semicon- ductor testing,

H. Xu and Z. Peng, “Active learning for spatial sampling in semicon- ductor testing,”IEEE Transactions on Semiconductor Manufacturing, vol. 34, no. 1, pp. 1–10, 2021

2021

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

[1] [1]

Farthest-point sampling for wafer-level variation modeling,

Y . Zhang and X. Liu, “Farthest-point sampling for wafer-level variation modeling,”IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 5, pp. 900–912, 2021

work page 2021

[2] [2]

C. E. Rasmussen and C. K. I. Williams,Gaussian Processes for Machine Learning. Cambridge, MA: MIT Press, 2006

2006

[3] [3]

Machine learning applications in semiconductor manufacturing: A review,

S. Lee, H. Wang, and K. K. Kim, “Machine learning applications in semiconductor manufacturing: A review,”Journal of Manufacturing Systems, vol. 57, pp. 468–484, 2020

work page 2020

[4] [4]

Optimizing test yield in semiconductor production through hybrid sampling techniques,

X. Li, Y . Zhang, and Y . Sun, “Optimizing test yield in semiconductor production through hybrid sampling techniques,”IEEE Transactions on Automation Science and Engineering, vol. 15, no. 4, pp. 1713–1723, 2018. 0 5 10 15 20 Wafer Index 0.030 0.035 0.040 0.045 0.050 0.055 0.060RMS Error Stratified vs S-SDE Stratified S-SDE 0 5 10 15 20 Wafer Index k-means...

work page 2018

[5] [5]

Advanced test strategies for semi- conductor wafer inspection using machine learning,

T. Nguyen, S. Hu, and Y . C. Chen, “Advanced test strategies for semi- conductor wafer inspection using machine learning,”IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 3, pp. 391–400, 2019

work page 2019

[6] [6]

Uncertainty-driven sampling for efficient wafer testing,

M. Chen and H. Mallick, “Uncertainty-driven sampling for efficient wafer testing,”IEEE Transactions on Computer-Aided Design of In- tegrated Circuits and Systems, vol. 40, no. 12, pp. 2450–2461, 2021

work page 2021

[7] [7]

Efficient wafer-level spatial variation modeling for multi-site rf IC testing,

M. R. ul Haqueet al., “Efficient wafer-level spatial variation modeling for multi-site rf IC testing,”IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E107-A, no. 8, pp. 1139–1150, 2024

work page 2024

[8] [8]

Wafer-level variation modeling for multi-site RF IC testing via hier- archical gaussian process,

M. Shintani, M. Inoue, T. Nakamura, M. Kajiyama, M. Eikiet al., “Wafer-level variation modeling for multi-site RF IC testing via hier- archical gaussian process,” inProceedings of the IEEE International Test Conference (ITC), 2021, pp. 103–112

work page 2021