CBM-Dual is the first silicon-proven 65-nm digital processor for a 1024-neuron chaotic Boltzmann machine that supports dual-mode simulated annealing and reservoir computing with 99% fewer operations and 59% less area via a custom scheduler and multiply splitting.
Yoshioka et al., ICFPT, pp
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UNVERDICTED 2representative citing papers
DORA is an instruction-based DNN accelerator architecture with a two-stage compilation framework that delivers stable efficiency across varied workloads and up to 5x throughput gains versus prior accelerators on FPGA.
citing papers explorer
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CBM-Dual: A 65-nm Fully Connected Chaotic Boltzmann Machine Processor for Dual Function Simulated Annealing and Reservoir Computing
CBM-Dual is the first silicon-proven 65-nm digital processor for a 1024-neuron chaotic Boltzmann machine that supports dual-mode simulated annealing and reservoir computing with 99% fewer operations and 59% less area via a custom scheduler and multiply splitting.
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DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration
DORA is an instruction-based DNN accelerator architecture with a two-stage compilation framework that delivers stable efficiency across varied workloads and up to 5x throughput gains versus prior accelerators on FPGA.