Networked bivariate bicycle QLDPC codes achieve competitive circuit-level performance to monolithic versions when Bell pair fidelity is high enough, based on Stim simulations with BP-OSD decoding.
(2023).Co-designed superconducting architecture for lat- tice surgery of surface codes with Quantum Interface Routing Card[Preprint]
6 Pith papers cite this work. Polarity classification is still indexing.
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A modular end-to-end simulation framework jointly models surface-code operations, QPU connectivity, and network constraints to produce execution latency and logical error rate estimates, revealing network-dependent operating regimes for distributed quantum computing.
Heterogeneous quantum architectures with task-specific hardware and QEC encodings deliver up to 138x lower physical-qubit overhead than monolithic baselines for fault-tolerant algorithms, including RSA-2048 factoring at 190k-381k qubits.
Three architectural types for fault-tolerant distributed quantum computing exhibit distinct scaling of Bell-pair consumption and generation attempts with code distance in planar surface and toric codes.
Simulations show non-local CNOT achieves up to 10x lower logical error than teleportation and distributed qLDPC needs d≈11 at p=10^{-4} or d≈29 at p=10^{-3} (with p_ebit=10p) for <10^{-12} error.
Proposes a fabless-foundry ecosystem for superconducting quantum chips built on certified PDKs, SPICE-Q multiphysics modeling, parameterized cells, Q-EDA automation, and a quantum-IP market.
citing papers explorer
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Networked Realization of Quantum LDPC Codes
Networked bivariate bicycle QLDPC codes achieve competitive circuit-level performance to monolithic versions when Bell pair fidelity is high enough, based on Stim simulations with BP-OSD decoding.
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Impact of Network Constraints on Fault-Tolerant Distributed Quantum Computing
A modular end-to-end simulation framework jointly models surface-code operations, QPU connectivity, and network constraints to produce execution latency and logical error rate estimates, revealing network-dependent operating regimes for distributed quantum computing.
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Heterogeneous architectures enable a 138x reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting
Heterogeneous quantum architectures with task-specific hardware and QEC encodings deliver up to 138x lower physical-qubit overhead than monolithic baselines for fault-tolerant algorithms, including RSA-2048 factoring at 190k-381k qubits.
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Architectural Approaches to Fault-Tolerant Distributed Quantum Computing and Their Entanglement Overheads
Three architectural types for fault-tolerant distributed quantum computing exhibit distinct scaling of Bell-pair consumption and generation attempts with code distance in planar surface and toric codes.
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Transversal Fault Tolerant Distributed Quantum Computing Operations
Simulations show non-local CNOT achieves up to 10x lower logical error than teleportation and distributed qLDPC needs d≈11 at p=10^{-4} or d≈29 at p=10^{-3} (with p_ebit=10p) for <10^{-12} error.
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Fabless Quantum Chip Design and Commercial Production
Proposes a fabless-foundry ecosystem for superconducting quantum chips built on certified PDKs, SPICE-Q multiphysics modeling, parameterized cells, Q-EDA automation, and a quantum-IP market.