Proposes a 10T SRAM XNOR in-memory computing architecture with 14T full adders that reduces routing complexity by 50% and improves area efficiency by 2.67x for BNN MAC operations.
A 5-nm 254-tops/w 221-tops/mm2 fully-digital computing-in-memory macro supporting wide-range dynamic-voltage- frequency scaling and simultaneous mac and write operations,
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SRAM Based Digital Custom Compute Engine for Improved Area Efficiency of AI Hardware
Proposes a 10T SRAM XNOR in-memory computing architecture with 14T full adders that reduces routing complexity by 50% and improves area efficiency by 2.67x for BNN MAC operations.