SRAM Based Digital Custom Compute Engine for Improved Area Efficiency of AI Hardware

Narendra Singh Dhakad; Santosh Kumar Vishvakarma

arxiv: 2605.16161 · v1 · pith:3UWZF4PDnew · submitted 2026-05-15 · 💻 cs.AR

SRAM Based Digital Custom Compute Engine for Improved Area Efficiency of AI Hardware

Narendra Singh Dhakad , Santosh Kumar Vishvakarma This is my paper

Pith reviewed 2026-05-19 18:24 UTC · model grok-4.3

classification 💻 cs.AR

keywords SRAMin-memory computingbinary neural networksXNORfull adderarea efficiencyAI accelerator

0 comments

The pith

A 10T SRAM cell with integrated full adders cuts routing complexity by half and raises area efficiency 2.67 times for binary neural network hardware.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a digital compute engine that performs XNOR-based multiply-accumulate operations directly inside a 10T SRAM array. Placing a full adder between multiplication cells trims interconnect length, while a compact 14T adder builds the tree that sums partial results. These changes target the routing bottlenecks that dominate conventional in-memory designs for binary networks. The result is lower latency per operation and smaller overall silicon area. If the measured savings hold, the approach offers a purely digital path to denser edge-AI accelerators.

Core claim

By using a 10T SRAM cell for XNOR computation and inserting a full adder directly between in-memory multiplication cells, the architecture achieves a 50 percent reduction in routing complexity; an additional 14T full adder constructs an N-bit ripple-carry adder tree, delivering a 2.67 times improvement in overall area efficiency relative to prior state-of-the-art designs for binary neural networks.

What carries the argument

10T SRAM XNOR cell with an inserted full adder that performs local accumulation inside the memory array.

Load-bearing premise

Integrating the full adder between in-memory cells produces the stated routing and area savings without adding unaccounted delay, power, or yield penalties once the circuit is fabricated.

What would settle it

Fabricate a test chip containing the proposed SRAM array and compare its measured silicon area and MAC latency against a re-implemented state-of-the-art baseline; the efficiency gain must fall below 2 times to falsify the central claim.

Figures

Figures reproduced from arXiv: 2605.16161 by Narendra Singh Dhakad, Santosh Kumar Vishvakarma.

**Figure 2.** Figure 2: shows the proposed architecture, combining a full adder with two cells of consecutive rows. The multiplication output of two rows is fed as inputs to the full adder. The 8- bit sum output is taken out to the adder tree, and carry is propagated through full adders in the column to get the final carry at the last bit. Finally, we will get a 9-bit output from two rows of SRAM. Bringing the full adder inside t… view at source ↗

**Figure 3.** Figure 3: Schematic of the read decoupled 10T SRAM cell [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗

**Figure 4.** Figure 4: Read operations for decoupled 10T SRAM cell [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗

**Figure 7.** Figure 7: Latency comparison of XNOR based multiplication for [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗

**Figure 8.** Figure 8: Latency and area comparisons reduced by 76%, which plays a significant contribution to the area efficiency of the macro [PITH_FULL_IMAGE:figures/full_fig_p004_8.png] view at source ↗

**Figure 9.** Figure 9: Layout of proposed IMC macro Con ven ti on al Proposed 0 1 0 20 30 40 50 60 A r e a E f fi ci e n c y ( T O P S / m m 2 ) Approach [PITH_FULL_IMAGE:figures/full_fig_p005_9.png] view at source ↗

**Figure 10.** Figure 10: Area efficiency comparison to the outside adder tree. For that, the architecture brings the adder inside the memory array, which reduces the routing conjunction by half and reduces the adder tree’s first accumulation effort. Hence, it reduces the latency and area of the SRAM array and adder tree. Also, we designed the adder tree using a small 14T based full adder, which further significantly reduces the … view at source ↗

read the original abstract

This paper presents a novel architecture utilizing a 10T SRAM cell for XNOR-based in-memory computing, aimed at mitigating the extensive routing challenges typically encountered in conventional in-memory computing systems. By integrating a full adder between in-memory multiplication cells, the proposed design achieves a 50% reduction in routing complexity. The architecture performs multiply-accumulate (MAC) operations using XNOR computation optimized for binary neural networks (BNNs). Additionally, a 14T-based full adder is employed to construct an N-bit ripple carry adder in the adder tree, significantly reducing the area compared to traditional 28T-based CMOS designs. The 10T SRAM XNOR computation further enhances the latency for MAC operations. The proposed approach reduces the latency and area overhead, improving the overall hardware's area efficiency by 2.67x compared to the state-of-the-art.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The 10T SRAM XNOR plus 14T adder integration is a concrete circuit tweak for cutting routing in BNN in-memory MAC, but the 2.67x area claim sits on unshown net savings.

read the letter

The paper's main move is a 10T SRAM cell that does XNOR in place and then drops a 14T full adder right next to it so the adder tree can eat some of the wiring that usually balloons in these arrays. That specific pairing and the shift to a ripple-carry tree built from the smaller adder look like the actual new piece; most prior in-memory BNN work either keeps the adder separate or uses standard 28T cells. The write-up does a clear job walking through how the local integration trims the long routes that normally dominate area in these engines, and the target—smaller silicon for binary nets on the edge—is the right one to chase. Credit for spelling out the transistor counts and the basic MAC flow without hiding behind vague diagrams. The soft spot is exactly where the stress-test flagged: the abstract and description assert a 50% routing drop and 2.67x overall area win versus SOTA, yet nothing in the supplied text shows post-layout extraction, parasitic numbers, or even a simple area table that subtracts the extra transistors and control overhead from the claimed savings. Without those, it is impossible to know whether the integration actually delivers net gain or just moves the cost elsewhere. This is the kind of paper circuit designers who already work on custom SRAM compute blocks would read for the cell-level idea. A reader who needs working silicon numbers or reproducible comparisons will come away empty. It is coherent on its own terms and shows honest engagement with the routing problem, so it clears the bar for a serious referee even though the quantitative headline still needs the missing verification steps. I would send it out rather than desk-reject.

Referee Report

2 major / 1 minor

Summary. The manuscript proposes a novel SRAM-based digital custom compute engine for AI hardware that employs a 10T SRAM cell for XNOR-based in-memory multiplication optimized for binary neural networks. By placing a full adder between in-memory multiplication cells, the design claims a 50% reduction in routing complexity; it further uses a 14T full adder to build an N-bit ripple-carry adder tree, asserting substantial area savings relative to conventional 28T CMOS implementations. The overall architecture is reported to reduce latency and area overhead, yielding a 2.67x improvement in hardware area efficiency compared with the state-of-the-art.

Significance. If the claimed routing and area reductions can be substantiated, the architecture would address a practical bottleneck in in-memory computing accelerators for BNNs. The explicit use of a reduced-transistor-count adder and the integration strategy for routing relief constitute a concrete, implementable proposal that could be evaluated against existing digital IMC baselines.

major comments (2)

[Abstract] Abstract: the quantitative assertions of a 50% routing reduction and 2.67x area-efficiency gain are presented without any supporting layout extraction, post-layout timing or power numbers, transistor-count breakdown, or comparison against the cited SOTA baseline, leaving the net savings after integration overheads unverified.
[Abstract] Abstract: the claim that inserting a full adder between XNOR cells produces a true 50% routing reduction does not address potential offsetting costs in control logic, additional interconnect capacitance, or process-variation effects on yield and delay; no analysis or simulation is supplied to demonstrate that these overheads do not erode the headline metric.

minor comments (1)

[Abstract] The phrase 'state-of-the-art' is used without naming the specific prior architectures or papers against which the 2.67x figure is measured.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript proposing the SRAM-based digital custom compute engine. We address each major comment point by point below and outline the revisions we will make to strengthen the presentation of our results.

read point-by-point responses

Referee: [Abstract] Abstract: the quantitative assertions of a 50% routing reduction and 2.67x area-efficiency gain are presented without any supporting layout extraction, post-layout timing or power numbers, transistor-count breakdown, or comparison against the cited SOTA baseline, leaving the net savings after integration overheads unverified.

Authors: The 50% routing reduction follows directly from replacing long global interconnects with local connections to the inserted full adders, as shown in the architecture diagram and explained in Section III. The 2.67x area-efficiency figure is obtained from a transistor-count comparison against the referenced SOTA digital IMC designs, using the 10T XNOR cell and 14T adder. We agree the abstract would benefit from clearer linkage to these supporting details. In the revised manuscript we will add an explicit transistor-count breakdown table and a short paragraph in the abstract summarizing the estimation methodology. revision: yes
Referee: [Abstract] Abstract: the claim that inserting a full adder between XNOR cells produces a true 50% routing reduction does not address potential offsetting costs in control logic, additional interconnect capacitance, or process-variation effects on yield and delay; no analysis or simulation is supplied to demonstrate that these overheads do not erode the headline metric.

Authors: The local placement of the 14T full adders is intended to avoid extra global control signals; the adders reuse the existing column-wise timing and do not introduce new control logic beyond standard word-line and bit-line drivers. Nevertheless, we recognize that a quantitative discussion of capacitance and variation effects would improve the paper. We will add a dedicated paragraph in the revised manuscript that qualitatively assesses these overheads and explains why they remain secondary to the routing savings for the targeted BNN workloads. revision: partial

Circularity Check

0 steps flagged

No circularity: descriptive hardware architecture with no derivations or fitted inputs

full rationale

The paper is a hardware architecture proposal describing a 10T SRAM XNOR cell, full-adder integration for routing reduction, and 14T adder tree. It states design choices and resulting claims (50% routing reduction, 2.67x area efficiency) without any equations, parameter fitting, self-referential definitions, or derivation chains. No load-bearing steps reduce to inputs by construction, self-citation, or renaming. The analysis is self-contained as an engineering description relying on standard CMOS and in-memory computing principles rather than circular reasoning.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The paper relies on standard VLSI and CMOS design assumptions without introducing new physical entities or free parameters; claims rest on architectural modifications to existing SRAM and adder structures.

axioms (1)

domain assumption Standard assumptions in VLSI design regarding transistor counts, routing overheads, and SRAM cell stability for 10T and 14T configurations
These underpin the comparisons to traditional 28T CMOS designs and the 50% routing reduction claim.

pith-pipeline@v0.9.0 · 5673 in / 1319 out tokens · 68245 ms · 2026-05-19T18:24:36.555901+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

11 extracted references · 11 canonical work pages

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Masset, R

G. Raut, A. Biasizzo, N. Dhakad, N. Gupta, G. Papa, and S. K. Vishvakarma, “Data multiplexed and hardware reused architecture for deep neural network accelerator,”Neurocomput., vol. 486, no. C, p. 147–159, may 2022. [Online]. Available: https://doi.org/10.1016/j. neucom.2021.11.018

work page doi:10.1016/j 2022
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A configurable 10t sram-based imc accelerator with scaled-voltage-based pulse count modulation for mac and high-throughput xac,

P. K. Saragada, S. Manna, A. Singh, and B. P. Das, “A configurable 10t sram-based imc accelerator with scaled-voltage-based pulse count modulation for mac and high-throughput xac,”IEEE Transactions on Nanotechnology, vol. 22, pp. 222–227, 2023

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8t xnor-sram based parallel compute- in-memory for deep neural network accelerator,

H. Jiang, R. Liu, and S. Yu, “8t xnor-sram based parallel compute- in-memory for deep neural network accelerator,” in2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, pp. 257–260

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Xnor-sram: In-memory computing sram macro for binary/ternary deep neural networks,

Z. Jiang, S. Yin, M. Seok, and J.-s. Seo, “Xnor-sram: In-memory computing sram macro for binary/ternary deep neural networks,” in2018 IEEE Symposium on VLSI Technology, 2018, pp. 173–174

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R- inmac: 10t sram based reconfigurable and efficient in-memory advance computation for edge devices,

N. S. Dhakad, E. Chittora, V . Sharma, and S. K. Vishvakarma, “R- inmac: 10t sram based reconfigurable and efficient in-memory advance computation for edge devices,”Analog Integrated Circuits and Signal Processing, vol. 116, no. 3, pp. 161–184, 2023

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X-sram: Enabling in- memory boolean computations in cmos static random access memories,

A. Agrawal, A. Jaiswal, C. Lee, and K. Roy, “X-sram: Enabling in- memory boolean computations in cmos static random access memories,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4219–4232, 2018

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M. Vesterbacka, “A 14-transistor cmos full adder with full voltage-swing nodes,” in1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No. 99TH8461). IEEE, 1999, pp. 713–722

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16.4 an 89tops/w and 16.3tops/mm2 all-digital sram-based full-precision compute-in memory macro in 22nm for machine-learning edge applications,

Y .-D. Chih, P.-H. Lee, H. Fujiwara, Y .-C. Shih, C.-F. Lee, R. Naous, Y .-L. Chen, C.-P. Lo, C.-H. Lu, H. Mori, W.-C. Zhao, D. Sun, M. E. Sinangil, Y .-H. Chen, T.-L. Chou, K. Akarvardar, H.-J. Liao, Y . Wang, M.-F. Chang, and T.-Y . J. Chang, “16.4 an 89tops/w and 16.3tops/mm2 all-digital sram-based full-precision compute-in memory macro in 22nm for mac...

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A multiply- less approximate sram compute-in-memory macro for neural-network inference,

H. Diao, Y . He, X. Li, C. Tang, W. Jia, J. Yue, H. Luo, J. Song, X. Li, H. Yang, H. Jia, Y . Liu, Y . Wang, and X. Tang, “A multiply- less approximate sram compute-in-memory macro for neural-network inference,”IEEE Journal of Solid-State Circuits, pp. 1–12, 2024

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Masset, R

G. Raut, A. Biasizzo, N. Dhakad, N. Gupta, G. Papa, and S. K. Vishvakarma, “Data multiplexed and hardware reused architecture for deep neural network accelerator,”Neurocomput., vol. 486, no. C, p. 147–159, may 2022. [Online]. Available: https://doi.org/10.1016/j. neucom.2021.11.018

work page doi:10.1016/j 2022

[2] [3]

A configurable 10t sram-based imc accelerator with scaled-voltage-based pulse count modulation for mac and high-throughput xac,

P. K. Saragada, S. Manna, A. Singh, and B. P. Das, “A configurable 10t sram-based imc accelerator with scaled-voltage-based pulse count modulation for mac and high-throughput xac,”IEEE Transactions on Nanotechnology, vol. 22, pp. 222–227, 2023

work page 2023

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8t xnor-sram based parallel compute- in-memory for deep neural network accelerator,

H. Jiang, R. Liu, and S. Yu, “8t xnor-sram based parallel compute- in-memory for deep neural network accelerator,” in2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, pp. 257–260

work page 2020

[4] [5]

Xnor-sram: In-memory computing sram macro for binary/ternary deep neural networks,

Z. Jiang, S. Yin, M. Seok, and J.-s. Seo, “Xnor-sram: In-memory computing sram macro for binary/ternary deep neural networks,” in2018 IEEE Symposium on VLSI Technology, 2018, pp. 173–174

work page 2018

[5] [6]

R- inmac: 10t sram based reconfigurable and efficient in-memory advance computation for edge devices,

N. S. Dhakad, E. Chittora, V . Sharma, and S. K. Vishvakarma, “R- inmac: 10t sram based reconfigurable and efficient in-memory advance computation for edge devices,”Analog Integrated Circuits and Signal Processing, vol. 116, no. 3, pp. 161–184, 2023

work page 2023

[6] [7]

A 4nm 6163-tops/w/b4790−TOPS/mm 2/b sram based digital-computing-in-memory macro supporting bit-width flexibility and simultaneous mac and weight update,

H. Mori, W.-C. Zhao, C.-E. Lee, C.-F. Lee, Y .-H. Hsu, C.-K. Chuang, T. Hashizume, H.-C. Tung, Y .-Y . Liu, S.-R. Wu, K. Akarvardar, T.- L. Chou, H. Fujiwara, Y . Wang, Y .-D. Chih, Y .-H. Chen, H.-J. Liao, and T.-Y . J. Chang, “A 4nm 6163-tops/w/b4790−TOPS/mm 2/b sram based digital-computing-in-memory macro supporting bit-width flexibility and simultaneo...

work page 2023

[7] [8]

A 5-nm 254-tops/w 221-tops/mm2 fully-digital computing-in-memory macro supporting wide-range dynamic-voltage- frequency scaling and simultaneous mac and write operations,

H. Fujiwara, H. Mori, W.-C. Zhao, M.-C. Chuang, R. Naous, C.-K. Chuang, T. Hashizume, D. Sun, C.-F. Lee, K. Akarvardar, S. Adham, T.- L. Chou, M. E. Sinangil, Y . Wang, Y .-D. Chih, Y .-H. Chen, H.-J. Liao, and T.-Y . J. Chang, “A 5-nm 254-tops/w 221-tops/mm2 fully-digital computing-in-memory macro supporting wide-range dynamic-voltage- frequency scaling ...

work page 2022

[8] [9]

X-sram: Enabling in- memory boolean computations in cmos static random access memories,

A. Agrawal, A. Jaiswal, C. Lee, and K. Roy, “X-sram: Enabling in- memory boolean computations in cmos static random access memories,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4219–4232, 2018

work page 2018

[9] [10]

A 14-transistor cmos full adder with full voltage-swing nodes,

M. Vesterbacka, “A 14-transistor cmos full adder with full voltage-swing nodes,” in1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No. 99TH8461). IEEE, 1999, pp. 713–722

work page 1999

[10] [11]

16.4 an 89tops/w and 16.3tops/mm2 all-digital sram-based full-precision compute-in memory macro in 22nm for machine-learning edge applications,

Y .-D. Chih, P.-H. Lee, H. Fujiwara, Y .-C. Shih, C.-F. Lee, R. Naous, Y .-L. Chen, C.-P. Lo, C.-H. Lu, H. Mori, W.-C. Zhao, D. Sun, M. E. Sinangil, Y .-H. Chen, T.-L. Chou, K. Akarvardar, H.-J. Liao, Y . Wang, M.-F. Chang, and T.-Y . J. Chang, “16.4 an 89tops/w and 16.3tops/mm2 all-digital sram-based full-precision compute-in memory macro in 22nm for mac...

work page 2021

[11] [12]

A multiply- less approximate sram compute-in-memory macro for neural-network inference,

H. Diao, Y . He, X. Li, C. Tang, W. Jia, J. Yue, H. Luo, J. Song, X. Li, H. Yang, H. Jia, Y . Liu, Y . Wang, and X. Tang, “A multiply- less approximate sram compute-in-memory macro for neural-network inference,”IEEE Journal of Solid-State Circuits, pp. 1–12, 2024

work page 2024