An FPGA prototype demonstrates real-time 30 MHz track reconstruction for the LHCb VELO detector by processing live experiment data.
A FPGA-based architecture for real-time cluster finding in the LHCb silicon pixel detector
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A real-time demonstrator of track reconstruction with FPGAs at LHCb
An FPGA prototype demonstrates real-time 30 MHz track reconstruction for the LHCb VELO detector by processing live experiment data.