A unified crossbar-based microarchitecture executes all RISC-V vector permutation instructions with fixed single-cycle latency at only 1.5% area overhead in a 7 nm processor.
Maximizing the potential of custom RISC-V vector extensions for speeding up SHA-3 hash functions,
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Efficient Implementation of RISC-V Vector Permutation Instructions
A unified crossbar-based microarchitecture executes all RISC-V vector permutation instructions with fixed single-cycle latency at only 1.5% area overhead in a 7 nm processor.