A proposed JPA gain-profile co-design aims to remove Purcell filters from superconducting readout, together with a low-power CMOS SoC receiver, both supported only by simulation.
Building Blocks of a Flip-Chip Integrated Superconducting Quantum Processor
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abstract
We have integrated single and coupled superconducting transmon qubits into flip-chip modules. Each module consists of two chips -- one quantum chip and one control chip -- that are bump-bonded together. We demonstrate time-averaged coherence times exceeding $90\,\mu s$, single-qubit gate fidelities exceeding $99.9\%$, and two-qubit gate fidelities above $98.6\%$. We also present device design methods and discuss the sensitivity of device parameters to variation in interchip spacing. Notably, the additional flip-chip fabrication steps do not degrade the qubit performance compared to our baseline state-of-the-art in single-chip, planar circuits. This integration technique can be extended to the realisation of quantum processors accommodating hundreds of qubits in one module as it offers adequate input/output wiring access to all qubits and couplers.
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Design of Advanced Readout and System-on-Chip Analog Circuits for Quantum Chip
A proposed JPA gain-profile co-design aims to remove Purcell filters from superconducting readout, together with a low-power CMOS SoC receiver, both supported only by simulation.