A bit-insertion formula for controlled-gate iteration indices reduces scheduled kernel iterations, giving up to about 7x speedup for control-heavy circuits on FPGAs.
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Optimising Iteration Scheduling for Full-State Vector Simulation of Quantum Circuits on FPGAs
A bit-insertion formula for controlled-gate iteration indices reduces scheduled kernel iterations, giving up to about 7x speedup for control-heavy circuits on FPGAs.