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REVIEW 3 major objections 5 minor 20 references

Optimising Iteration Scheduling for Full-State Vector Simulation of Quantum Circuits on FPGAs

T0 review · 3 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read This paper claims that an index-mapping formula can schedule exactly the memory iterations a controlled quantum gate needs, delivering up to 7x faster FPGA simulation on circuits with many controls.

desk verdict Scheduling trick is real and the speedups are credible, but the energy-efficiency headline leans on unmeasured power ratings and the core index-mapping formula is a known bit-deposit operation. read the letter →

arxiv 2411.18354 v1 pith:GQLMCHP5 submitted 2024-11-27 quant-ph cs.AR

Youssef Moawad , Andrew Brown , René Steijl , Wim Vanderbauwhede This is my paper · ORCID
classification quant-phcs.AR
keywords quantumcircuitsimulationFPGAaccelerationfull-state-vectorcontrolledgatesiterationschedulingmemoryaccesspatternenergyefficiency
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that an FPGA quantum simulator can run much faster by scheduling only the memory iterations that a gate actually needs, with the gate's control qubits taken into account. The standard kernel schedules $2^{n-1}$ pair accesses for every gate and then tests whether each pair satisfies the controls; on an FPGA those tests leave statically scheduled memory cycles unused. The paper derives an index-mapping formula, Equation 5, that sends each index in the reduced set $[0,2^{n-n_c-1}-1]$ to its correct global iteration index, where $n_c$ is the number of controls on the gate. As a result the control-flow guard can be removed and every scheduled iteration performs a useful memory access. The authors report almost $2\times$ lower simulation time on squaring circuits and almost $7\times$ on streaming circuits, and they argue this makes FPGA simulation competitive with CPU and GPU platforms in energy efficiency, which is the main constraint on scaling full-state-vector simulation.

What carries the argument

The central object is the iteration index set of a gate: the list of indices fed to the pair-indexing function that locates the two amplitudes to read and write. The baseline set is $I_g=[0,2^{n-1}-1]$; the optimised set is $I_r=[0,2^{n-n_c-1}-1]$, and the load-bearing identity is Equation 5, the iterative skip map built from adjusted control positions and skip intervals $2^{c_{\mathrm{adj}}}$. Its job is to reconstruct the unique global iteration index for each reduced index, replacing a dynamic control-flow check with static integer arithmetic. Because FPGA memory cycles are scheduled statically, this substitution is what turns skipped iterations into time savings rather than wasted clock cycles.

What would settle it

For a register of $n=5$ to $n=10$ qubits, enumerate every target qubit and every strictly ascending control set, run the optimised kernel on a random state vector, and compare the exact pairs read and written against a reference kernel that checks controls directly; any mismatch would falsify the central claim. In parallel, measure the FPGA board's real power draw during the 29-qubit streaming circuit; if the measured energy no longer beats the CPU and GPU totals, the energy-efficiency conclusion fails.

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Extended reading notes

Core claim

The central discovery is that the pair of amplitudes touched by a controlled gate is completely determined by a closed-form map from the reduced iteration set to the global iteration set. For each control qubit $c$, the paper defines an adjusted control $c_{\mathrm{adj}}=c-1$ when $c>t$ and $c_{\mathrm{adj}}=c$ otherwise, and the skip interval $2^{c_{\mathrm{adj}}}$; the map is applied iteratively, once per control, in strictly ascending control order, using $i_{r_k}=i_{r_{k+1}}+(\lfloor i_{r_{k+1}}/2^{c_{\mathrm{adj}}}\rfloor+1)2^{c_{\mathrm{adj}}}$. This sends every index of $[0,2^{n-n_c-1}-1]$ to the unique index of $[0,2^{n-1}-1]$ that the baseline kernel would need, so the runtime check on controls can be dropped. The paper demonstrates the pattern on 3- and 4-qubit access tables and reports FPGA time reductions of roughly $2\times$ for QFT and squaring circuits and $7\times$ for streaming circuits, with the optimised kernel using essentially the same FPGA resources as the baseline.

Load-bearing premise

The argument depends on the unproven pattern claim that Equation 5 maps the reduced iteration set to the correct global iteration set for every target qubit and every strictly ascending control set; if any configuration gives the wrong global index, the optimised kernel would read and write the wrong amplitude pairs.

Editorial extensions

If this is right

  • For a gate with $n_c$ controls, scheduled iterations fall from $2^{n-1}$ to $2^{n-n_c-1}$, so each additional control halves the work the simulator performs.
  • On FPGAs, where memory-access cycles are statically scheduled, the removed guard time translates directly into wall-clock gains: the paper measures almost $2\times$ for QFT and squaring circuits and almost $7\times$ for streaming circuits.
  • The optimised kernel uses nearly the same FPGA resources as the baseline and runs at a slightly higher maximum frequency, so the speedup is obtained without an area cost.
  • Energy per simulation falls in the same proportion as time under the rated-power model; in the streaming case the FPGA's total energy is below both the CPU and GPU totals reported by the authors.
  • Because streaming circuits contain gates with up to $n-1$ controls, they demonstrate the method's best case; any circuit dominated by multi-controlled gates would inherit this benefit.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A natural extension is to apply the same skip map to negative controls, where the control condition is satisfied by $|0\rangle$ rather than $|1\rangle$; the access-pattern symmetry in Figure 4 suggests the formula would only change which global indices are selected.
  • The formula's correctness is shown by exhaustive small-register patterns rather than a proof, so an independent check over all targets and ascending control sets for $n=5$ through $n=10$ would directly test whether it generalises.
  • Because the reduced iteration count shortens the serial gate schedule itself, combining this optimisation with multiple compute units, gate fusion, or fixed-point arithmetic should compound the savings rather than merely add to them.
  • The energy comparison multiplies measured runtimes by rated power values, so a direct power measurement on the FPGA board during the streaming circuit would show whether the claimed energy advantage over CPU and GPU holds under real operating conditions.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper presents a scheduling optimization for full-state-vector simulation of quantum circuits on FPGAs. Instead of always scheduling 2^(n-1) iterations for an n-qubit gate, the authors propose Eq. (5), an index-mapping formula that maps a reduced iteration set [0, 2^(n-nc-1)-1] to the global iteration set, taking into account the gate's control qubits. This reduces the number of scheduled kernel iterations that perform memory accesses to only those required by the controlled gate. The method is evaluated on three circuit families (QFT, squaring, streaming) using FPGA, CPU, and GPU OpenCL implementations. The reported results show speedups up to about 7x for the streaming circuit on the FPGA and, under the paper's energy model, the FPGA is claimed to outperform CPU and GPU in energy efficiency for that circuit.

Significance. If the scheduling formula and its generalization hold, the contribution is practically useful: it is a parameter-free transformation that removes wasted memory-access scheduling for controlled gates on FPGAs, while leaving resource usage essentially unchanged (Table I). The paper has the strength of implementing the method in a real OpenCL kernel and evaluating it on nontrivial circuits. However, the headline energy-efficiency claim is not established by the data as presented, because it relies on unmeasured rated power values rather than actual power measurements, and the generalization of Eq. (5) from small examples to arbitrary n and control sets is asserted without proof. The core scheduling idea is credible and worth publishing after these concerns are addressed.

major comments (3)
  1. [Section IV, Tables II-IV] The energy-efficiency claim is not supported by the evidence. The paper computes energy as measured runtime multiplied by rated power: 25 W for the FPGA, 160 W for the CPU, and 250 W for the GPU. No wattmeter measurements, on-board power monitoring, or repeated runs are reported. For the 29-qubit streaming circuit (Table IV), the FPGA advantage over the GPU disappears if the FPGA board draws more than roughly 63 W on average, and the rated-power values for CPU/GPU are likely worst-case thermal design powers. Thus the conclusion that the FPGA 'allows to outperform both CPU and GPU platforms in terms of energy efficiency' is not established at the claimed confidence.
  2. [Section III-B, Eq. (5)] Eq. (5) is the core contribution, but the paper provides only worked examples for 3- and 4-qubit registers. There is no general proof that the iterative formula is a bijection from [0, 2^(n-nc-1)-1] to the subset of global iteration indices that satisfy the controls, for arbitrary n, arbitrary target qubit t, and arbitrary ascending control sets. Since the correctness of the entire optimization depends on this mapping, a proof or at least a rigorous inductive argument is needed.
  3. [Abstract and Conclusion] The abstract and conclusion state that the approach 'allows to outperform both CPU and GPU platforms in terms of energy efficiency.' The data in Tables II and III show that the GPU has lower energy than the FPGA for both the QFT and the squaring circuits; the claimed advantage appears only for the streaming circuit. The paper should either restrict the claim to the streaming case or provide a broader energy evaluation supporting the general statement.
minor comments (5)
  1. [Author affiliations] The affiliation 'University of Glagow' appears to be a typo for 'University of Glasgow'; this should be corrected.
  2. [Eq. (2)] In Eq. (2) the summation runs from k=0 to 2^n, but for an n-qubit state vector the index range should be 0 to 2^n - 1. This is likely a typo.
  3. [Eq. (5) and surrounding text] The displayed equation uses floor notation, but the worked examples write expressions like '0/1 + 1' without floor brackets. It would be clearer to explicitly use integer division or floor notation in the examples.
  4. [Section IV-D] The statement that the architecture 'could run on up to 4x smaller FPGA' and thereby achieve better energy efficiency is speculative, since no resource or power measurements for such a device are provided.
  5. [Figure 4] The sentence 'which again can is verified by the figure' contains a grammatical error; it should read 'which can again be verified by the figure.'

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the iteration-scheduling formula is an algorithmic construction validated against measured baselines, and the energy claim rests on stated input assumptions rather than fitted outputs.

full rationale

The paper's central claim is the iteration-scheduling formula in Eq. 5, which maps a reduced iteration index set to the global index set based on adjusted control-qubit positions. This is an algorithmic construction, not a prediction defined in terms of the result; it is checked against explicitly enumerated examples in Figure 4 and implemented directly in OpenCL. The reported speedups are measured comparisons between a baseline kernel and the optimized kernel on the same hardware, and the energy numbers are computed by multiplying measured runtimes by stated rated power values (25 W FPGA, 160 W CPU, 250 W GPU). Those power figures are input assumptions, not fitted parameters or outputs of the measured system, so even though they are a fragility of the energy-efficiency claim, they do not make the derivation circular. The paper does cite the authors' earlier work [13] for the squaring circuits and for a fuller related-work summary, but that citation is not load-bearing for the new scheduling technique: the optimization is evaluated independently against a baseline implementation and external benchmarks, and its correctness does not depend on the cited prior work. No step in the derivation reduces by construction to its own inputs, and no fitted quantity is renamed as a prediction. The absence of a proof that Eq. 5 generalizes beyond the tested patterns is a rigor limitation, not circularity. Overall, the derivation chain is self-contained with respect to the paper's stated contribution.

Assumptions & free parameters 1 free parameters · 5 assumptions · 0 invented entities

The scheduling claim itself is self-contained and uses no fitted parameters; the only input constants are hardware power ratings. The main burden is the unproved generalization of Eq. 5 and the use of rated rather than measured power in the energy comparison.

free parameters (1)
  • Device power consumption ratings = FPGA: 25 W, CPU: 160 W, GPU: 250 W
    Used to convert measured runtimes into energy; taken from rated values rather than measured, so the energy comparison depends on these hand-chosen numbers.
assumptions (5)
  • ad hoc to paper The pattern in Figure 4 generalizes to arbitrary n, target, and ascending controls, so Eq. 5 is a valid bijection.
    No general proof or induction is given; the formula is inferred from small examples in Section III-B.
  • domain assumption Controls are supplied in strictly ascending order: c0 < c1 < ...
    Stated as the only condition for Eq. 5; circuits must be preprocessed to ensure this.
  • domain assumption Only positive controls (control bit = 1) are considered.
    The kernel checks the bit equals 1; negative controls are mentioned in the introduction but not supported.
  • domain assumption Rated power is a valid proxy for actual power draw during simulation.
    Energy = runtime x rated power in Section IV; no power measurements are reported.
  • domain assumption The ithCleared function from [7] correctly returns the lower element index of each pair.
    The whole iteration mapping is built on this external indexing function, which is cited but not re-derived.

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Cite this review

Pith. "Pith review of Optimising Iteration Scheduling for Full-State Vector Simulation of Quantum Circuits on FPGAs." pith.science (2026). https://pith.science/paper/GQLMCHP5

@misc{pith2026241118354,
  author       = {Pith},
  title        = {Pith review of: Optimising Iteration Scheduling for Full-State Vector Simulation of Quantum Circuits on FPGAs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/GQLMCHP5}},
  note         = {Machine review of arXiv:2411.18354}
}
read the original abstract

As the field of quantum computing grows, novel algorithms which take advantage of quantum phenomena need to be developed. As we are currently in the NISQ (noisy intermediate scale quantum) era, quantum algorithm researchers cannot reliably test their algorithms on real quantum hardware, which is still too limited. Instead, quantum computing simulators on classical computing systems are used. In the quantum circuit model, quantum bits (qubits) are operated on by quantum gates. A quantum circuit is a sequence of such quantum gates operating on some number of qubits. A quantum gate applied to a qubit can be controlled by other qubits in the circuit. This applies the gate only to the states which satisfy the required control qubit state. We particularly target FPGAs as our main simulation platform, as these offer potential energy savings when compared to running simulations on CPUs/GPUs. In this work, we present a memory access pattern to optimise the number of iterations that need to be scheduled to execute a quantum gate such that only the iterations which access the required pairs (determined according to the control qubits imposed on the gate) are scheduled. We show that this approach results in a significant reduction in the time required to simulate a gate for each added control qubit. We also show that this approach benefits the simulation time on FPGAs more than CPUs and GPUs and allows to outperform both CPU and GPU platforms in terms of energy efficiency, which is the main factor for scalability of the simulations.

Figures

Figures reproduced from arXiv: 2411.18354 by the authors.

Figure 1
Figure 1. Illustration of simple two-qubit quantum circuits. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Memory access pattern example for 3-qubit full state [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Full state vector gate simulation kernel pseudocode. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (7 more)
Figure 5
Figure 5. Figure 5: Implementation of the iterative formula for going from [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 4
Figure 4. Figure 4: Access patterns for controlled gate applications for [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 6
Figure 6. Figure 6: Example 5-qubit QFT circuit [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 7
Figure 7. Figure 7: Total energy consumption of QFT circuits. [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]
Figure 10
Figure 10. Figure 10: Total energy consumption of streaming circuits. [PITH_FULL_IMAGE:figures/full_fig_p006_10.png]
Figure 8
Figure 8. Figure 8: Total energy consumption of SQ circuits. [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 9
Figure 9. Figure 9: 4-qubit streaming circuit. A general n-qubit streaming circuit can be constructed in the same pattern, which will contain gates with up to n − 1 controls [PITH_FULL_IMAGE:figures/full_fig_p006_9.png]

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Reference graph

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