An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
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A modular atomic processor with 500,000 qubits factors 2048-bit RSA numbers in roughly the same time as a single large module when inter-module Bell-pair communication runs at 10^5 per second.
The paper introduces concrete code deformation procedures for dense surface code packing, proposes hook-error-avoiding CNOT scheduling for syndrome extraction, and reports Monte Carlo simulations showing lower logical error rates than standard surface codes at large distances and low physical error,
citing papers explorer
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Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder
An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
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Factoring $2048$ bit RSA integers with a half-million-qubit modular atomic processor
A modular atomic processor with 500,000 qubits factors 2048-bit RSA numbers in roughly the same time as a single large module when inter-module Bell-pair communication runs at 10^5 per second.
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Dense packing of the surface code: code deformation procedures and hook-error-avoiding gate scheduling
The paper introduces concrete code deformation procedures for dense surface code packing, proposes hook-error-avoiding CNOT scheduling for syndrome extraction, and reports Monte Carlo simulations showing lower logical error rates than standard surface codes at large distances and low physical error,