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arxiv: 2511.06758 · v2 · pith:UE7JNNRYnew · submitted 2025-11-10 · 🪐 quant-ph

Dense packing of the surface code: code deformation procedures and hook-error-avoiding gate scheduling

Kohei Fujiu , Shota Nagayama , Shin Nishio , Hideaki Kawaguchi , Takahiko Satoh This is my paper

Pith reviewed 2026-05-21 20:05 UTC · model grok-4.3

classification 🪐 quant-ph
keywords surface codedense packingcode deformationhook errorssyndrome extractionfault-tolerant quantum computingquantum error correctionlogical error rate
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0 comments X

The pith

Dense surface code packing with hook-error-avoiding scheduling achieves lower logical error rates than standard layouts while reducing physical qubit overhead.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper develops explicit procedures to deform separate surface code patches into a compact connected lattice that requires roughly three-quarters as many physical qubits as side-by-side placement. It supplies a CNOT scheduling for stabilizer measurements that prevents hook errors from spreading across the tight geometry. Circuit-level Monte Carlo simulations demonstrate that the logical error rate of the resulting dense code falls below the rate of an ordinary surface code once distance grows and physical error rate drops. The improvement holds only when the scheduling avoids hook errors; without that step the dense version performs worse despite the space savings. A reader would care because surface codes are the leading approach to fault-tolerant quantum computation but still demand impractically large numbers of physical qubits.

Core claim

By applying a sequence of code deformation steps that merge multiple standard surface code patches into a single densely packed configuration and then using a tailored CNOT gate schedule during syndrome extraction, the densely packed surface code simultaneously reduces the number of physical qubits per logical qubit to approximately three-fourths and, at sufficiently large code distances and sufficiently low physical error rates, exhibits a lower logical error rate than the standard surface code.

What carries the argument

Hook-error-avoiding CNOT scheduling for stabilizer measurements in the densely packed lattice, which blocks correlated error propagation that would otherwise arise from the compact geometry.

If this is right

  • Space overhead for surface-code fault tolerance drops to about 75 percent of conventional patch layouts.
  • Logical error rates improve relative to standard surface codes when physical error rates are low and distances are large.
  • Dynamic microarchitectures can reconfigure patches into dense form on demand without permanent qubit loss.
  • Stabilizer measurement circuits must incorporate the specific hook-avoiding schedule to realize any advantage.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The deformation procedures could be adapted to other planar topological codes that admit similar merging operations.
  • Hardware implementations may need additional calibration routines to maintain the exact timing required by the dense schedule.
  • If the scheduling generalizes cleanly, it could be combined with other overhead-reduction techniques such as flag-based error detection.

Load-bearing premise

The code deformation steps can be executed on hardware without adding connectivity or timing costs that erase the simulated error-rate advantage, and the Monte Carlo noise model captures the dominant errors of the target device.

What would settle it

An experiment or simulation at distance 9 or higher and physical error rate below 0.5 percent in which the logical error rate of the dense code with hook-error-avoiding scheduling exceeds the logical error rate of a standard surface code of the same distance.

Figures

Figures reproduced from arXiv: 2511.06758 by Hideaki Kawaguchi, Kohei Fujiu, Shin Nishio, Shota Nagayama, Takahiko satoh.

Figure 1
Figure 1. Figure 1: shows a patch of the surface code. In this configuration, physical qubits are arranged on a two￾dimensional lattice. The black dots denote physical data qubits, while the white dots represent the auxiliary qubits used for syndrome measurements, which we refer to as measurement qubits. The regions delineated by squares and triangles represent stabilizer generators. Here, dark￾shaded areas correspond to X-ty… view at source ↗
Figure 2
Figure 2. Figure 2: (a) shows the single X-type stabilizer genera￾tor excerpted, illustrating required two-qubit gates be￾tween data qubits and an measurement qubit for the syn￾drome measurement to perform the syndrome extraction [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. An example of the hook error in a syndrome extrac [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: illustrates how hook errors in the patch extend the length of error chains. In this case, X errors occurring on the measurement qubits of the X-type stabilizer gen￾erators propagate to the data qubits, turning two phys￾ical errors into four physical errors. Because the errors align with the logical X operator in the patch, a logical X error can occur with just two physical errors, despite the original code… view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. An example of densely packed [ [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Code deformation procedures to extend and contract [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. A layout of standalone surface code patches with [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Densely packed surface codes. The individual code [PITH_FULL_IMAGE:figures/full_fig_p005_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. A layout for a microarchitecture with hierarchical [PITH_FULL_IMAGE:figures/full_fig_p006_10.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12. The constraints for gate scheduling in surface codes. [PITH_FULL_IMAGE:figures/full_fig_p007_12.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11. The squares in the figure are schematic represen [PITH_FULL_IMAGE:figures/full_fig_p007_11.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13. Hook-error-avoiding gate scheduling for stan [PITH_FULL_IMAGE:figures/full_fig_p007_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: FIG. 14. Gate scheduling for densely packed surface codes. A, B, C, and D represent the order in which the gates are applied. [PITH_FULL_IMAGE:figures/full_fig_p008_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: FIG. 15. The densely packed patch encoding 5-logical qubits [PITH_FULL_IMAGE:figures/full_fig_p008_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: FIG. 16. Simulation results of logical error rates of surface codes with different configurations. The horizontal axis shows the [PITH_FULL_IMAGE:figures/full_fig_p009_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: FIG. 17. Code deformation procedure for dense packing of the surface code [PITH_FULL_IMAGE:figures/full_fig_p012_17.png] view at source ↗
Figure 17
Figure 17. Figure 17: FIG. 17. Code deformation procedure for dense packing of the surface code [PITH_FULL_IMAGE:figures/full_fig_p013_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: FIG. 18. Row-shifting movement in the densely packed surface code. [PITH_FULL_IMAGE:figures/full_fig_p015_18.png] view at source ↗
read the original abstract

The surface code is one of the leading quantum error correction codes for realizing large-scale fault-tolerant quantum computing (FTQC). One major challenge in realizing surface-code-based FTQC is the extremely large number of qubits required. To mitigate this problem, fusing multiple codewords of the surface code into a densely packed configuration has been proposed. It is known that by using dense packing, the number of physical qubits required per logical qubit can be reduced to approximately three-fourths compared to simply placing surface-code patches side by side. Despite its potential, concrete deformation procedures and quantitative error-rate analyses have remained largely unexplored. In this work, we present a detailed code-deformation procedure that transforms multiple standard surface code patches into a densely packed, connected configuration, along with a conceptual microarchitecture to utilize this dense packing. We also propose a CNOT gate-scheduling for stabilizer measurement circuits that suppresses hook errors in the densely packed surface code. We performed circuit-level Monte Carlo noise simulation of densely packed surface codes using this gate scheduling. The numerical results demonstrate that as the code distance of the densely packed surface code increases and the physical error rate decreases, the logical error rate of the densely packed surface code becomes lower than that of the standard surface code. Furthermore, we find that only when employing hook-error-avoiding syndrome extraction can the densely packed surface code achieve a lower logical error rate than the standard surface code, while simultaneously reducing the space overhead.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents explicit code-deformation procedures that fuse multiple standard surface-code patches into a connected, densely packed layout, reducing the physical-qubit overhead per logical qubit to roughly three-quarters of the conventional side-by-side arrangement. It introduces a CNOT gate-scheduling rule for stabilizer extraction that suppresses hook errors in the dense geometry and reports circuit-level Monte Carlo simulations under depolarizing noise showing that, with this scheduling, the logical error rate of the dense code falls below that of a standard surface code of equal distance once the physical error rate is sufficiently low and the distance is increased.

Significance. If the reported error-rate advantage survives more realistic modeling of deformation overheads, the work would provide a concrete route to lowering the space cost of surface-code FTQC while preserving or improving logical performance. The explicit deformation sequences and the demonstration that hook-error avoidance is essential for the advantage constitute useful, falsifiable contributions that can be checked by independent simulators.

major comments (2)
  1. §5 (Monte Carlo simulations): the circuits used for the dense-packing deformation steps are simulated without additional error channels, longer stabilizer cycles, or routing delays that would accompany the deformation on hardware. Because the central claim is that the dense code eventually outperforms the standard code at large distance and low p, the absence of these costs is load-bearing; a quantitative estimate or sensitivity analysis of the extra error rate per deformation round is required to substantiate the crossover.
  2. §4.3 (hook-error-avoiding scheduling): the paper states that only the proposed scheduling yields a lower logical error rate than the standard surface code, yet the results section does not present a direct side-by-side comparison (e.g., a table or overlaid plot) of logical error rates for the same dense geometry with and without the hook-avoiding schedule at multiple distances. This comparison is necessary to isolate the scheduling contribution from the packing itself.
minor comments (2)
  1. Figure 2: the microarchitecture diagram would benefit from an explicit legend indicating which qubits are data, ancilla, and routing qubits in the dense configuration.
  2. §3.2: the description of the deformation sequence would be clearer if each step were accompanied by a small circuit diagram showing the instantaneous stabilizer measurements.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the careful reading and constructive feedback on our manuscript. We address each major comment below and outline the revisions we intend to make to strengthen the presentation and support for our claims.

read point-by-point responses

  1. Referee: §5 (Monte Carlo simulations): the circuits used for the dense-packing deformation steps are simulated without additional error channels, longer stabilizer cycles, or routing delays that would accompany the deformation on hardware. Because the central claim is that the dense code eventually outperforms the standard code at large distance and low p, the absence of these costs is load-bearing; a quantitative estimate or sensitivity analysis of the extra error rate per deformation round is required to substantiate the crossover.

    Authors: We agree that the current simulations model the deformation steps using the same depolarizing noise as steady-state syndrome extraction, without explicitly incorporating additional error channels, extended cycle times, or routing delays. This simplification was chosen to isolate the impact of the dense geometry and scheduling rule. However, we recognize that a quantitative assessment of these overheads is important to substantiate the reported crossover at large distance and low physical error rate. In the revised manuscript we will add a sensitivity analysis: we will introduce a tunable extra error probability per deformation round (or per additional cycle) and show how the logical-error-rate curves shift, identifying the range of overhead values for which the dense code still outperforms the standard surface code. This will make the robustness of the advantage explicit. revision: yes

  2. Referee: §4.3 (hook-error-avoiding scheduling): the paper states that only the proposed scheduling yields a lower logical error rate than the standard surface code, yet the results section does not present a direct side-by-side comparison (e.g., a table or overlaid plot) of logical error rates for the same dense geometry with and without the hook-avoiding schedule at multiple distances. This comparison is necessary to isolate the scheduling contribution from the packing itself.

    Authors: We appreciate the referee’s observation. While the abstract and the discussion in §4.3 state that the hook-error-avoiding schedule is required for the dense code to achieve lower logical error rates than the standard surface code, we did not include an explicit comparative figure or table in the results section. We will revise the manuscript to add a direct side-by-side comparison—specifically an overlaid plot of logical error rate versus physical error rate for the dense geometry under both standard and hook-error-avoiding scheduling—at several distances. This addition will clearly separate the contribution of the scheduling rule from the effect of the dense packing itself. revision: yes

Circularity Check

0 steps flagged

No circularity: results from independent Monte Carlo simulations of proposed procedures

full rationale

The paper's central claims rest on circuit-level Monte Carlo noise simulations of the proposed code deformation procedures and hook-error-avoiding gate scheduling. These numerical results are generated from explicit circuit constructions under a depolarizing noise model rather than from any algebraic derivation, fitted parameter, or self-citation chain that reduces to the target logical-error-rate comparison by construction. No equations are presented that equate a prediction to an input fit, and the deformation procedures are described at the logical level without invoking prior self-cited uniqueness theorems or ansatzes that would force the reported advantage. The work is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work relies on standard assumptions of circuit-level noise simulations in quantum error correction but does not introduce new physical postulates or fitted constants beyond the usual physical error rate inputs.

axioms (1)
  • domain assumption Standard depolarizing circuit-level noise model governs the Monte Carlo simulations
    Invoked to generate the reported logical error rates for both packed and standard codes.

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Forward citations

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