A 0.18 µm CMOS clock-less bit-serial LVDS link using LEDR and token-ring serialization transmits 35.7 million AER events per second with power that scales only with event rate.
A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (DYNAPs),
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A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems
A 0.18 µm CMOS clock-less bit-serial LVDS link using LEDR and token-ring serialization transmits 35.7 million AER events per second with power that scales only with event rate.