A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems

Giacomo Indiveri; Ning Qiao

REVIEW 2 major objections 5 minor 19 references

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems

T0 review · 2 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read A clock-less LVDS link for neuromorphic chips achieves 35.7 million events per second at 1.5 Gbps, with power that scales linearly down to nanowatt idle levels.

desk verdict A credible measured demonstration of a clock-less LVDS link with event-rate-proportional power; the architecture is sound, but the missing bit-error-rate and timing-margin data leave the 1.5 Gbps reliability claim unquantified. read the letter →

arxiv 1908.06532 v1 pith:2ENDY3VC submitted 2019-08-18 cs.ET

Ning Qiao , Giacomo Indiveri This is my paper · ORCID

classification cs.ET

keywords Address-EventRepresentationLVDSasynchronousdesignLEDRencodingtoken-ringserializerneuromorphicmulti-chipsystemsevent-drivenpowerscalingbit-seriallink

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper aims to show that a bit-serial link for sending address-events between neuromorphic chips can be made fully asynchronous, eliminating the clock-recovery circuits (CDR with PLL/DLL) that normally dominate power and area. It encodes data in Level-Encoded Dual-Rail (LEDR), a two-wire scheme where each bit is self-timing, and serializes and deserializes through token-rings on both ends. The link is switched on only for the duration of an event burst and off between events by pulling the LVDS common-mode voltage to ground. Measured in 0.18 µm CMOS, the prototype reaches 35.7 million 32-bit events per second at 1.5 Gbps, and its power consumption tracks the event rate, with an idle floor of 80 nA on the transmitter and 42 nA on the receiver. A reader would care because large multi-chip neuromorphic systems currently use wide parallel AER buses; a low-power bit-serial link could replace them without sacrificing latency.

What carries the argument

The central mechanism is LEDR (Level-Encoded Dual-Rail) encoding combined with token-ring serializers on both transmitter and receiver. LEDR sends each bit on a data rail and a parity rail, alternating phases so that the receiver can tell bit boundaries by whether the two rails are equal; this makes the protocol delay-insensitive and removes the need for a forwarded clock. The transmitter token-ring encodes parallel event bits into LEDR order, the receiver token-ring decodes them back, and a tunable delay in the transmitter token-ring enforces the timing assumption that the receiver ring can consume each bit within one transmitter bit cycle. Instant on/off is achieved by pulling the LVDS common-mode voltage to ground between events, which switches off the receiver amplifier, and restoring it to a reference voltage at the start of an event.

What would settle it

Measure the bit-error rate of the link while sweeping the tunable delay and the supply voltage and temperature, and observe at what margin bits start being dropped, especially at the wake-up edge when the common-mode voltage is still recovering; a failure at a specific delay would show that the RX-token-ring throughput assumption is not robust.

Watch

Extended reading notes

Core claim

The central claim is that a clock-less LEDR-based bit-serial LVDS link can deliver high event throughput while making power strictly event-rate-dependent. Using two LVDS pairs (data and parity) with four-phase handshaking and token-ring serializers, the design avoids any CDR, PLL, or DLL: bit boundaries are recovered from the D=P versus D≠P relation of LEDR. The paper reports measured results from a 0.18 µm CMOS test chip: 1.5 Gbps bit rate, 35.7 MEvents/s for 32-bit events, 31 ns chip-to-chip latency, sub-0.5 ns wake-up/sleep, 0.14 mm² area, and a leakage-dominated idle current floor of 80 nA on the transmitter and 42 nA on the receiver, with linear power scaling down to a sub-µA level around 1k events/s.

Load-bearing premise

The design assumes the receiver token-ring can always absorb each transmitted bit within the transmitter's bit cycle, and this is guaranteed only by a tunable delay in the transmitter; the paper does not measure how much timing margin remains across supply voltage, temperature, and process corners.

Editorial extensions

If this is right

Multi-chip neuromorphic systems could replace wide parallel AER buses with a single bit-serial link, cutting pin count and I/O area.
Because power scales with event rate, sparse event traffic—the typical case in neural systems—costs almost nothing, with idle current in the tens of nanoamps.
The 31 ns chip-to-chip latency and sub-0.5 ns wake-up mean there is no lock-recovery wait for each event burst.
The compact 0.14 mm² block could be tiled as a building block in core-to-core or chip-to-chip routers.
The full-rate, non-return-to-zero nature of LEDR allows 1.5 Gbps without a clock, higher than the 0.64 Gbps of a comparable previous AER bit-serial link under test.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the timing margin of the token-ring handoffs is the real constraint, the same architecture should scale to smaller CMOS nodes only if the tunable delay can track process variations; this can be tested by measuring bit-error rate versus the delay setting.
The common-mode instant on/off trick could be reused in other low-duty-cycle serial links beyond AER, such as wireline sensor networks, since it converts standby power into leakage only.
A direct comparison against a clocked CDR link at equal bit rate and same process would quantify how much area and power the CDR actually costs; the paper notes such figures are missing from the prior designs it compares against.
One could extend the design to variable bit widths or flit-level control flow by adding more token-cells, without changing the encoding.

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Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short version: this is a real chip paper with one genuine new idea and mostly solid measurements. The instant on/off via common-mode voltage (0V idle, ~1V active) for the LVDS drivers and receivers is clever, and the measured 80nA/42nA idle floor plus linear scaling of power with event rate is a useful data point for neuromorphic multi-chip systems. The 35.7 MEvents/s, 1.5 Gbps numbers look plausible from the oscilloscope captures. The paper is honest about what it does: it is an empirical demonstration, not a fit to a target, and the self-citations are background.

Soft spots, in order of importance. First, link integrity is not actually measured. There is no bit-error-rate number, no eye diagram, no jitter measurement, and no sweep of the tunable delay td that enforces the central timing assumption in Section II.D — that the RX token-ring always finishes sampling a bit before the TX advances. The per-word acknowledge signal only tells you the RX ring completed a word, not that each bit was sampled with the correct value. Without a BER or a loopback test comparing sent to received data, the 1.5 Gbps claim is a waveform observation, not a validated link. Second, there is an internal inconsistency: the abstract assigns 19.3mA to the receiver and 3.57mA to the transmitter, while Section IV says the opposite. That needs to be resolved; it matters for anyone comparing the two blocks. Third, the feature list says 'sub-nW' static power for what is 220nW total, which is actually sub-µW. Minor copy error, but very visible. Fourth, there are no PVT corners or multi-chip statistics; I would not expect a full characterization in a short conference-style paper, but for a journal version it is necessary.

The stress-test note worries that the RX-throughput assumption is load-bearing and unmeasured. I think that is exactly right, and I would not call it manufactured. It is the main reason I cannot take the 1.5 Gbps integrity claim at face value. The rest of the architecture — LEDR encoding, token-ring serializer, common-mode wake-up — holds together, and the measurements support the power story.

Who should read this: people building tiled neuromorphic systems that need compact low-power inter-chip links, and asynchronous serial-link designers. It deserves a serious referee: the contribution is real and the flaws are fixable. I would send it to review with a request for BER/eye/timing-margin data (or at least a loopback test) and correction of the three internal errors. My verdict: conditional accept.

Referee Report

2 major / 5 minor

Summary. The paper presents a clock-less, fully asynchronous bit-serial LVDS link for Address-Event Representation (AER) multi-chip systems. The link is built on Level-Encoded Dual-Rail (LEDR) encoding and token-ring transmitter/receiver architectures, and it avoids conventional CDR blocks with PLL/DLL circuits. A prototype fabricated in 0.18 um CMOS occupies 0.14 mm^2. The authors report a 1.5 Gbps bit rate, an event rate of 35.7 MEvents/s for 32-bit events, and rate-dependent power consumption with a low-rate floor of 80 nA for the transmitter and 42 nA for the receiver. The central claim is that the proposed link is the first such AER bit-serial LVDS interface with no CDR/PLL/DLL, instant on/off, and power that scales linearly with event rate.

Significance. If the timing robustness is established, this is a significant contribution to neuromorphic multi-chip interfacing: it demonstrates a compact 0.14 mm^2, fully asynchronous bit-serial LVDS link without CDR/PLL/DLL, with measured sub-uA idle power and a large dynamic power range. The power-versus-rate curve is a designed architectural property and is verified by measurement, not extracted as a fit to the data, so there is no circularity in the power claim. However, the headline data-rate and event-rate claims are not yet backed by a direct measure of data integrity, and one internal inconsistency in the headline current numbers needs to be resolved before the results can be fully trusted.

major comments (2)

[II.D and IV] The headline rate claim rests on the unverified assumption stated in Section II.D that the RX token-ring always has higher throughput than the TX token-ring, enforced only by the tunable delay td. The paper reports no bit-error-rate (BER) measurement, no sweep of td around the nominal 0.67 ns bit cycle, no jitter or eye-diagram data, and no process/voltage/temperature corner characterization. The acknowledge signal out.a is a per-word handshake and does not verify that every bit was sampled with the correct value, so the 1.5 Gbps / 35.7 MEvents/s claim is not yet backed by an end-to-end data-integrity metric. Please add a BER measurement over a statistically meaningful number of bits, a td margin sweep, and at least a statement of the measured timing margin.
[Abstract and Section IV] The two most prominent numerical claims are internally inconsistent: the abstract assigns 19.3 mA to the receiver and 3.57 mA to the transmitter, while Section IV states the opposite. Table I's Pmax value of 22.9 mA is the sum of the two and does not disambiguate the assignment. Please correct the order and ensure that the abstract, Section IV, and Table I all report the same block-level current consumption.

minor comments (5)

[II.A] The displayed equations for the LEDR encoding are printed with the odd-phase and even-phase cases identical because the overbars are missing; as printed they contradict the prose that specifies the parity rail as the inverted bit value in the even phase. Please restore the overbars so the definition is unambiguous.
[I and IV] The introduction claims 'Sub-nW (220nW) static power consumption', but 220 nW is sub-uW, not sub-nW. The measured 80 nA plus 42 nA at 1.8 V gives approximately 220 nW, so the label should be corrected to sub-uW.
[IV] The measurement methodology for the current/power values in Figure 16 is not described. Please state how the supply currents were measured, which blocks were included, the averaging window, and the number of measurements, and add error bars or measurement precision.
[IV] The paper states that the peak event rate is 'the peak event rate that can be achieved in our experimental setup'; please clarify whether the link itself or the test setup (neural array, router, or pipelining control queue) is the limiting element, and how the 28 ns event period relates to the 25.6 ns active transmission time for a 32-bit event.
[Table I and II] The relationship between the 1.5 Gbps bit rate, 32-bit events, and 35.7 MEvents/s event rate is not explicitly defined. A 32-bit payload at 1.5 Gbps would nominally take about 21.3 ns, while the measured period is 28 ns; the difference should be explained in terms of protocol overhead, wake-up time, and handshake timing.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the central claims are supported by direct chip measurements, with self-citations confined to background context.

full rationale

The paper's central claims are empirical demonstrations on a fabricated 0.18 µm CMOS chip: a 1.5 Gbps bit rate, a 35.7 MEvents/s event rate, and rate-dependent power consumption with sub-µA floors. These numbers come from oscilloscope captures and power measurements, not from a derivation that fits the target. The LEDR encoding and token-ring architecture are adopted from prior work ([15] and [16]), and self-citations to the authors' earlier systems appear only as background motivation or application context, not as load-bearing justification for the new link's performance. The statement that the RX token-ring is required to have the highest throughput and that a tunable delay Td enforces this timing assumption is a design constraint, not a circular reduction. The power-versus-rate curve is a designed property of the clock-less architecture and is verified by measurement; no fitted parameter is renamed as a prediction. The absence of a BER measurement or PVT corner sweep is a robustness concern, but it is a correctness/validation gap, not circularity. The comparison against external implementations in Table I is independent evidence. Overall, no step in the paper reduces by construction to its own inputs.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The central claim depends on two design-tuned parameters (bit delay and common-mode reference) and on standard asynchronous protocol assumptions. No new physical entity is postulated; the common-mode wake-up signaling is a re-use of existing wires, not an invented mediator.

free parameters (2)

bit cycle delay td = 0.67 ns
Set by tuning the delay cell in the TX token-ring (Section IV) to reach the 1.5 Gbps bit rate; all reported peak event rate, power, and latency numbers depend on this design choice.
LVDS common-mode reference Vref = about 1 V
Chosen as the receiver wake-up threshold (Section II-C); the instant on/off behavior and the receiver power figures depend on it.

assumptions (4)

domain assumption LEDR is a delay-insensitive protocol: bit boundaries are recoverable from D=P versus D≠P on two rails.
Invoked in Section II.A to justify removing CDR; it is an established property from [15], not re-derived in this paper.
ad hoc to paper The RX token-ring is always faster than the TX token-ring, enforced by tunable delay Td.
Stated in Section II.D: "In this design the RX Token-Ring is required to have the highest throughput." If this fails, bits are not absorbed within one TX bit cycle.
domain assumption When common-mode voltage returns to Vref with D=P, the NMOS-input LVDS receiver is fully turned on and ignores spurious repeated LSBs.
Analog behavior assumed in Sections II.C and IV; only demonstrated for one test setup, not across corners.
domain assumption Token cells are mutually exclusive and each cell is disabled only by its successor.
Standard asynchronous token-ring property from [16], used in Sections II.B and III.A.

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Cite this review

Pith. "Pith review of A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems." pith.science (2026). https://pith.science/paper/2ENDY3VC

@misc{pith2026190806532,
  author       = {Pith},
  title        = {Pith review of: A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/2ENDY3VC}},
  note         = {Machine review of arXiv:1908.06532}
}

read the original abstract

We present a power efficient clock-less fully asynchronous bit-serial Low Voltage Differential Signaling (LVDS) link with event-driven instant wake-up and self-sleep features, optimized for high speed inter-chip communication of asynchronous address-events between neuromorphic chips. The proposed LVDS link makes use of the Level-Encoded Dual-Rail (LEDR) representation and a token-ring architecture to encode and transmit data, avoiding the use of conventional large ClockData Recovery (CDR) modules with power-hungry DLL or PLL circuits. We implemented the LVDS circuits in a device fabricated with a standard 0.18 um CMOS process. The total silicon area used for such block is of 0.14 mm^2. We present experimental measurement results to demonstrate that, with a bit rate of 1.5 Gbps and an event width of 32-bit, the proposed LVDS link can achieve transmission event rates of 35.7 M Events/second with current consumption of 19.3 mA and 3.57 mA for receiver and transmitter blocks, respectively. Given the clock-less and instant on/off design choices made, the power consumption of the whole link depends linearly on the data transmission rate. We show that the current consumption can go down to sub-uA for low event rates (e.g., <1k Events/second), with a floor of 80 nA for transmitter and 42 nA for receiver, determined mainly by static off-leakage currents.

Figures

Figures reproduced from arXiv: 1908.06532 by the authors.

**Figure 1.** Encoding example of LEDR. Shaded regions represent the even phase and the non-shaded regions represent the odd phase. multi-chip neuromorphic systems. The paper is organized as follows: Section II presents the data transmission scheme and link architecture; Section III describes the circuits implementation of the proposed bit-serial LVDS link; Section IV presents the measurements made with the prototype chip and des… view at source ↗

**Figure 2.** A typical 8-bit transceiver based on token-ring archi [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Architecture of the proposed bit-serial LVDS link. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

Figures from the paper (11 more)

**Figure 4.** Figure 4: Proposed signaling scheme with LVDS for data [PITH_FULL_IMAGE:figures/full_fig_p003_4.png]

**Figure 6.** Figure 6: Transmitter Token-Ring for encoding data into [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]

**Figure 7.** Figure 7: Circuit implementation of the TX token-cell based on a [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]

**Figure 8.** Figure 8: Circuit implementation of the “TX LVDS Driver”. [PITH_FULL_IMAGE:figures/full_fig_p005_8.png]

**Figure 9.** Figure 9: Receiver Token-Ring for decoding data/phase to event [PITH_FULL_IMAGE:figures/full_fig_p005_9.png]

**Figure 12.** Figure 12: Die photo of test chip with proposed event-driven bit [PITH_FULL_IMAGE:figures/full_fig_p006_12.png]

**Figure 11.** Figure 11: LVDS Receiver for digitizing differential [PITH_FULL_IMAGE:figures/full_fig_p006_11.png]

**Figure 13.** Figure 13: The setup for testing LVDS links between two chips for bidirectional communication [PITH_FULL_IMAGE:figures/full_fig_p007_13.png]

**Figure 15.** Figure 15: Transient signals of LVDS pairs at receiver inputs: (a) differential mode of LVDS signals, (b) acknowledge signal from the receiver, (c) details of single event transmission signals. LV DS1_P were used to transmit events from Chip1 to Chip2, and LV DS2_D and LV DS2_P …

**Figure 14.** Figure 14: Transient signals of LVDS pairs captured on the receiver’s inputs: the traces D. f and D.t represent the differential signals for LV DS_D; the traces P. f and P.t represent the differential signals for LV DS_P; The D_Di f f and P_Di f f traces are differential voltag…

**Figure 16.** Figure 16: Power consumption of asynchronous serial-bit [PITH_FULL_IMAGE:figures/full_fig_p008_16.png]

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Reference graph

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Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.

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