A simulated racetrack-memory in-memory CNN accelerator using write-to-shift conversion and shift-based multipliers achieves up to 83.5x energy-efficiency improvement and 1.68x performance gain over an unoptimized 8-bit fixed-point baseline.
A signed binary multiplication technique
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Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems
A simulated racetrack-memory in-memory CNN accelerator using write-to-shift conversion and shift-based multipliers achieves up to 83.5x energy-efficiency improvement and 1.68x performance gain over an unoptimized 8-bit fixed-point baseline.