Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems

Benjamin Chen Ming Choong; Bingsheng He; Cheng Liu; Joey Tianyi Zhou; Tao Luo; Wei Zhang

REVIEW 4 major objections 5 minor 74 references

Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems

T0 review · 4 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read A racetrack-memory CNN accelerator claims up to 83.5x lower energy and 1.68x higher performance for 8-bit inference by replacing magnetic writes with cheap shift operations and co-optimizing model and memory.

desk verdict Solid circuit-level ideas in a simulation-only RM accelerator; headline energy gains hinge on an unvalidated 20x write/shift ratio. read the letter →

arxiv 2507.01429 v1 pith:37JZXBSC submitted 2025-07-02 cs.ET cs.AIcs.AR

Benjamin Chen Ming Choong , Tao Luo , Cheng Liu , Bingsheng He , Wei Zhang , Joey Tianyi Zhou This is my paper · ORCID

classification cs.ETcs.AIcs.AR

keywords ArtificialIntelligenceHardware-softwareCo-designDeepLearningEmbeddedSystemsEmergingMemoryRacetrackIn-memorycomputingCNNinference

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Racetrack memory stores bits in magnetic domains that can be shifted past a read/write port like a shift register; this paper argues that those shifts can do real arithmetic, not just move data. The central trick is to avoid the most expensive operation, writing a magnetic tunnel junction, by instead shifting a preloaded '0' or '1' into place, since a modeled write costs about 20 times more energy than a shift. Combined with a multiplier that performs logarithmically quantized (power-of-two) weights as shifts instead of generating partial products, the paper reports up to 83.5x better energy efficiency and 1.68x higher performance for 8-bit CNN inference compared with an unoptimized 8-bit fixed-point baseline, with accuracy loss of a few percent. If the device numbers hold, small CNN models could run entirely inside racetrack memory, avoiding the off-chip transfers that dominate energy in embedded systems.

What carries the argument

The carrying mechanism is the write-shift transformation: each input magnetic tunnel junction in an adder is paired with a three-bit racetrack preloaded with magnetization patterns for '1' and '0', so changing the required input bit is done by shifting the track until the right pattern sits under the junction, consuming 0.051 pJ of shift energy instead of a 1 pJ write, and nothing when the bit is unchanged. The second mechanism is the shift-based multiplier, which reuses the same shift-enable/disable idea: a CMOS decrementing counter per weight controls which tracks shift in each cycle, so logarithmically quantized activations align themselves during access and are accumulated by a bit-serial full adder without ever writing partial products. The macro unit, a layout interleaving four racetrack strips and access transistors, carries the data-reuse strategy: all four tracks shift together and share one weight, giving four parallel multiplications per access.

What would settle it

Measure the energy of toggling a single input to an MTJ-based full adder through the three-bit shift track over many cycles; if the average toggle energy is materially above 0.051 pJ per bit, the reported 94.4% adder energy reduction and the 83.5x system-level gain would not survive.

Watch

Extended reading notes

Core claim

On the paper's own terms, the discovery is that racetrack memory's natural shift operation can be turned into an arithmetic enabler rather than an access overhead. The proposed circuits are magnetic-tunnel-junction half and full adders with fewer junction writes than prior magnetic adders, a Booth multiplier for ordinary fixed-point models, and a shift-based multiplier that aligns power-of-two products by selectively enabling and disabling each track's shift circuitry under a decrementing counter. The write-shift transformation equips each computation junction with a tiny three-bit track so an input bit is delivered by shifting the needed '0' or '1' into place, and consecutive identical bits cost no energy. In system-level simulation, this lowers arithmetic energy by up to 94.4% per adder, and combined with logarithmically quantized weights and a memory layout that reuses weights across the four tracks of a macro unit, the accelerator reports 83.5x energy-efficiency gain and 1.68x speedup on 8-bit ResNet-20 inference with a 3.2% accuracy loss.

Load-bearing premise

The headline savings assume that writing a racetrack bit costs roughly 20 times more energy than shifting it (1 pJ versus 0.051 pJ), and that the three-bit shift tracks feeding each adder junction can be operated reliably at that energy.

Editorial extensions

If this is right

If the write-shift transformation works at the modeled energies, arithmetic energy in racetrack-memory adders drops by about 94%, and system-level energy becomes dominated by memory access rather than by computation.
Logarithmically quantized models with shift distance ±7 can be executed with over 70% lower energy on LeNet-5 and over 90% lower energy on ResNet-20 than their Booth-based fixed-point counterparts, with accuracy loss below 10%.
For embedded-scale models that fit in a single bank (LeNet-5 and ResNet-20), the accelerator can run the whole inference on-chip, avoiding the off-chip transfers that dominate conventional CNN accelerators.
On ResNet-20, combining the write-shift optimization with shift-based multiplication gives the headline 83.5x energy-efficiency and 1.68x performance improvements relative to unoptimized 8-bit fixed-point execution.
For large models such as VGG-16, batching inputs to size 8 or more reduces DRAM transfers by over 70%, but on-chip write energy remains the dominant cost, so the largest savings appear on models that fit on-chip.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the real device write-to-shift energy ratio is closer to 5x than to the modeled 20x, the 94.4% adder savings and the headline 83.5x would shrink in roughly proportional fashion; a sensitivity sweep across this ratio would be a cheap way to test how robust the conclusion is.
Because the paper notes that skyrmion racetracks share the same shift-and-access interface, the same write-shift transformation could plausibly be ported to skyrmion devices, though skyrmion readability is not yet solved.
Because the shift control is a small CMOS counter, the shift distance could in principle be exposed as a runtime software knob, letting a deployed device trade accuracy for energy on a per-inference basis; the paper does not explore this dynamic control.
The reported 83.5x gain comes from a model that fits in one bank, so applying the same comparison to a large model with significant DRAM traffic would almost certainly yield a smaller multiple, a direction the paper's own VGG-16 results already suggest.

Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Worth a look if you work on racetrack-memory in-memory computing. The genuinely new pieces are the selective shift-enable multiplier and the write-shift transformation. The multiplier improves on DWMAcc by cutting pad bits, supporting sign extension and both shift directions, and replacing the alignment stage with simple counter-controlled enable/disable logic. The write-shift transformation is a neat trick: instead of writing a new bit into an adder's MTJ, you shift a pre-stored bit on a tiny auxiliary track into place. In simulation this cuts full-adder energy by 94.4%. Those are real extensions, not just re-packaged prior work.

The paper also does the system-level homework. The accelerator architecture is described in enough detail to follow the dataflow, the NVSim and SPICE methodology is transparent, and the authors are honest that the write-shift optimization is mainly an energy optimization, not a latency one. The Booth and adder circuits come from their own prior papers, which is fine; the contribution here is the integration and the new optimization.

The soft spot is exactly where the reader and stress-test put it: the headline 83.5x energy improvement rests on the 20x write/shift energy ratio in Table 2. Shift energy of 0.051 pJ comes from modeling works for a 64-domain racetrack, but the proposed auxiliary track is a 3-bit structure with its own overhead regions; nobody has shown that ratio transfers. No sensitivity analysis is provided. If the real ratio were 5x, the adder saving drops to roughly half and the shift-based multiplier advantage over Booth narrows proportionally. The 83.5x number is a single-point estimate, not a robust claim. A second real gap is the absence of a same-framework comparison against DWMAcc or another published racetrack accelerator; the baseline is their own unoptimized fixed-point design, which is legitimate but limits context. The simulator is not released, so the numbers are hard to check independently.

None of this kills the architecture idea. The circuit concepts are sound and the paper is honest about its assumptions. But the quantitative claims should be treated as simulation-based upper bounds until the device parameters are validated or at least sensitivity-analyzed. The paper deserves a serious referee: an expert can assess whether the 3-bit track can realistically shift at that energy, and the authors should be pushed to release the simulator and add a DWMAcc comparison. I'd take it to reading group and would cite it if I were writing on RM-based in-memory arithmetic, but I would not put the 83.5x number in a survey without a caveat.

Referee Report

4 major / 5 minor

Summary. The paper presents an in-memory CNN accelerator built on racetrack memory (RM), comprising RM-based half/full adders, a Booth multiplier, a shift-based multiplier, and a 'write-shift transformation' that replaces energy-expensive MTJ writes with cheaper shift operations. The authors integrate these arithmetic units into a multi-bank RM memory system with a specific data mapping for CNN layers, and they co-explore model quantization (linear and logarithmic) and system configurations across LeNet-5, ResNet-20, and VGG-16. Using SPICE circuit simulations, NVSim memory modeling, and a custom system-level simulator, they report up to 83.5x improved energy efficiency and 1.68x better performance for 8-bit CNN models relative to their unoptimized 8-bit fixed-point implementation.

Significance. If the results are robust, the paper makes a meaningful contribution to in-memory computing with emerging racetrack memory: it shows how the intrinsic shift operation of RM can be exploited both for shift-based neural network models and for replacing write operations in arithmetic circuits. The methodology is largely transparent: component energies come from SPICE and NVSim, operation counts are derived from the dataflow description, and the authors explicitly state that the write-shift transformation is mainly an energy optimization. A notable strength is that the headline claims are not obtained by fitting parameters to the target results; they follow from a transparent combination of measured component energies and operation counts. However, the central quantitative claims depend critically on the modeled write/shift energy ratio in Table 2, which is not validated and receives no sensitivity analysis, making the reported savings a single-point estimate. The paper also builds on the authors' own prior adder and Booth multiplier designs without clearly delineating the new contributions in this manuscript.

major comments (4)

[§3.4, Table 2, §5.1.1, Fig. 35] The write-shift energy optimization and the resulting 94.4% adder-energy reduction (Section 5.1.1) and the system-level 83.5x efficiency improvement (Fig. 35) are all directly inherited from the assumption that a racetrack write costs approximately 20x more energy than a shift (1 pJ vs 0.051 pJ in Table 2). The paper provides no sensitivity analysis over this ratio, nor over the absolute shift energy, and the shift-energy value is taken from modeling works for a 64-domain racetrack [62,65] and applied without validation to the proposed 3-bit auxiliary track with overhead regions. If the real write/shift energy ratio is materially smaller or the 3-bit track cannot be shifted reliably at the modeled energy, the central efficiency advantage collapses proportionally. Please add a sensitivity analysis over the write/shift energy (and latency) ratio and the actual energy of shifting the short auxiliary track, and discuss the impact on the 83.5x and 94.4% claims.
[§3.1 and §3.2] The adder circuits and Booth multiplier are presented as part of this work's contribution, but the text opens Section 3.1 with 'we illustrate energy-efficient MTJ-based half adder and full adder circuits [33,34]', and prior self-citations [33,34,31] cover the Booth multiplier and adder. The abstract states 'we design a series of fundamental arithmetic circuits,' which overstates the novelty if those circuits were already published. The manuscript must clearly separate prior contributions of the authors from the new contributions of this paper (e.g., the shift-based multiplier, the write-shift transformation, and the system-level integration), so that the novelty claim is evaluable.
[§5.2.4, Fig. 35] The headline '83.5x better energy efficiency and 1.68x higher performance' for ResNet-20 is reported as a ratio without giving the absolute energy and latency values for the three compared configurations (8b No W-S, 8b W-S, Shift). The axes of Fig. 35 are not readable in the text, and the exact definition of the efficiency metric (presumably frames/J, possibly normalized by area) is not stated. Please provide a table with the absolute energy, latency, throughput, and area-normalized efficiency numbers for all three configurations, along with the explicit formula used to compute the 83.5x and 1.68x ratios.
[§5.2] The system-level simulator is described only as 'we developed a simulator to assess the total energy and latency of an inference pass' and the results are given without the aggregation equations or assumptions for interleaving, position-reset phases, duplicate activations, and bank-level adder-tree communication. To make the system-level results reproducible and auditable, please specify the equations and dataflow parameters used to combine SPICE and NVSim numbers into the reported totals, including how the position-reset cycles and the duplicate-activation overhead are included.

minor comments (5)

[Throughout] The manuscript contains numerous typographical and grammatical errors, including 'a obstacle' in the Introduction, 'With characteristicsof' in Section 3.3, and 'the enable logicto besimple' in the same section. A thorough proofreading pass is needed.
[Section 3.4] The sentence 'the full adder is synchronous and depends on pulses of the system clock, which remains bound by write operations in MU storage' is confusing; clarify that the write-shift transformation reduces energy but does not reduce the critical-path latency because the system clock must still accommodate write operations in the storage array.
[Section 5.1.2] In Fig. 23, the Booth multiplier energy is reported as 'energy per bit' but the text is not explicit about whether the write-shift overhead (shift-control circuitry energy) is included in the optimized curve; please clarify the energy breakdown.
[Section 6] The comparison with prior skyrmion/racetrack logic works [29,3] claims that 'our bit-serial 8-bit full adder outperforms those reported in [29] (latency, energy, area)' but no quantitative comparison table is provided. Adding a table with the specific numbers would strengthen the related-work discussion.
[Table 2] Since the write energy of 1 pJ and shift energy of 0.051 pJ are the linchpin of the claimed savings, the sources and modeling assumptions for these parameters should be stated more prominently, and the applicability of these values to the specific 3-bit auxiliary track should be discussed.

Circularity Check

0 steps flagged · score 2.0 of 10

No circular derivation: the reported energy/latency savings are computed from stated device parameters and simulated operation counts; the only self-citations (prior adder/Booth designs, racetrack model) are not load-bearing.

full rationale

The derivation chain is: device parameters in Table 2 (write=1 pJ, shift=0.051 pJ) produce SPICE-level adder/multiplier energies (Section 5.1), then NVSim memory-array energies (Section 4.1), then a system simulator that counts MAC operations per CNN layer (Section 5.2), leading to the headline 83.5x energy efficiency and 1.68x performance (Fig. 35). No step fits a parameter to the claim being predicted. The 94.4% adder-energy reduction is the arithmetic consequence of replacing 7 MTJ writes by 7 shifts in the full adder (7.019 pJ to 0.392 pJ, i.e., 7*(1-0.051) pJ plus logic energy); the 83.5x for ResNet-20 similarly follows from the simulator's energy model and per-layer operation counts. The write/shift energy ratio is an external device assumption from [62]/[65], not a fitted output, so the absence of sensitivity analysis is a robustness and validity concern, not circularity. Self-citations do exist: Sections 3.1-3.2 build on the authors' prior adder and Booth designs [33,34], and the racetrack model [62] has co-author overlap (Wei Zhang). These are not load-bearing: the circuits are re-specified with schematics and re-evaluated via SPICE in Section 5.1, and the racetrack model is an independent parameterized modeling paper whose assumptions do not include the present efficiency result. No uniqueness theorem is imported and no known result is merely renamed. The central claim therefore stands on the paper's own simulation chain; the score of 2 reflects only the minor self-citation, not any circular reduction.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The central efficiency claim depends on device parameters borrowed from prior models, on NVSim and a private simulator, and on hand-selected quantization and architecture configurations. The new hardware elements are concretely specified circuits rather than unexplained entities.

free parameters (4)

Linear quantization scale x_max = Chosen from powers of two 1 to 32 per model and bit-width to maximize validation accuracy
Selection occurs in Section 5.2.1 and shapes the reported accuracy and the bit-width choices.
Model activation bit-width for reported configurations = LeNet-5: 4-bit; ResNet-20: 8-bit; VGG-16: 8-bit
These are the co-exploration outcomes that underlie the 83.5x and 1.68x claims; other bit-widths have different gains.
Logarithmic shift distance d_s = +-7 for all recommended models
Section 5.2.4 selects +-7 as the configuration with under 10% accuracy loss; the energy and latency improvements are tied to this.
VGG-16 batch size = 8
Section 5.2.5 selects batch size 8 to balance DRAM access savings and latency; the reported VGG-16 efficiency uses this choice.

assumptions (5)

domain assumption Racetrack memory write energy is 1 pJ and shift energy is 0.051 pJ, as given in Table 2.
The write-shift optimization and most reported energy savings are computed directly from this ratio; the paper cites [62,65] for the device model.
domain assumption NVSim accurately models racetrack memory banks configured with MU parameters.
Bank area and access energy are taken from NVSim, and no silicon measurement is provided for the full system.
domain assumption The prior adder and Booth multiplier circuits [33,34] are correct and form the basis of the claimed arithmetic units.
Section 3.1 attributes the adders to these self-cited papers; the new work builds on them without re-deriving the base circuits.
domain assumption LogQuant [27] post-training quantization provides realistic CNN accuracy for linear and logarithmic weight quantization.
All accuracy tables and the selection of shift distance +-7 rely on this method.
domain assumption The custom simulator includes all relevant dynamic energy, including computation, read, write, shift, and DRAM energy.
Section 5.2 asserts this, but source code is not available to verify the accounting.

how reviews work

0 comments

Cite this review

Pith. "Pith review of Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems." pith.science (2026). https://pith.science/paper/37JZXBSC

@misc{pith2026250701429,
  author       = {Pith},
  title        = {Pith review of: Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/37JZXBSC}},
  note         = {Machine review of arXiv:2507.01429}
}

read the original abstract

Deep neural networks generate and process large volumes of data, posing challenges for low-resource embedded systems. In-memory computing has been demonstrated as an efficient computing infrastructure and shows promise for embedded AI applications. Among newly-researched memory technologies, racetrack memory is a non-volatile technology that allows high data density fabrication, making it a good fit for in-memory computing. However, integrating in-memory arithmetic circuits with memory cells affects both the memory density and power efficiency. It remains challenging to build efficient in-memory arithmetic circuits on racetrack memory within area and energy constraints. To this end, we present an efficient in-memory convolutional neural network (CNN) accelerator optimized for use with racetrack memory. We design a series of fundamental arithmetic circuits as in-memory computing cells suited for multiply-and-accumulate operations. Moreover, we explore the design space of racetrack memory based systems and CNN model architectures, employing co-design to improve the efficiency and performance of performing CNN inference in racetrack memory while maintaining model accuracy. Our designed circuits and model-system co-optimization strategies achieve a small memory bank area with significant improvements in energy and performance for racetrack memory based embedded systems.

Figures

Figures reproduced from arXiv: 2507.01429 by the authors.

**Figure 1.** Basic structure of vertical magnetic tunnel junction (top) and magnetic nanowire of racetrack memory (bottom). short, magnetized units termed domains, each of which store a bit of information [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 3.** Visualization of a convolution layer. The result of MAC operations of the Filter 1 at the highlighted input position is the red output activation in output channel 1, whereas that of Filter F is the blue output activation in output channel F. 2.2. Convolutional Neural Networks (CNN) 2.2.1. Computation in CNN The largest and most computation-intensive layers of a CNN are typically the convolution layers, in which hig… view at source ↗

**Figure 4.** Schematic of the proposed half adder. = (𝐼0 >> 2) + 𝐼1 + (𝐼2 << 3) (2) In order to gain computational savings, these shift-andadd operations must be executed on shifting logic rather than full-precision multipliers. As racetrack memory offers natural support for shift operations, this work explores an efficient implementation of shift-based models as well. The shifting circuitry of racetrack memory can align data u… view at source ↗

Figures from the paper (25 more)

**Figure 5.** Figure 5: Schematic of the proposed full adder. FA0 𝐴2 𝐴1 𝑆 𝐶𝑜𝑢𝑡 𝐶𝑖𝑛 𝑦0 𝑥0 Cycle 1 Inputs 𝑥0 and 𝑦0 written to adder. FA0 𝐴2 𝐴1 𝐶𝑜𝑢𝑡 𝑆 𝐶𝑖𝑛 FA1 𝐴2 𝐴1 𝐶𝑜𝑢𝑡 𝑆 𝐶𝑖𝑛 𝑦0 𝑥0 𝑦1 𝑥1 𝑧0 𝑧1 FA2 𝐴2 𝐴1 𝐶𝑜𝑢𝑡 𝑆 𝐶𝑖𝑛 𝑦2 𝑥2 𝑧2 𝑐0 𝑐1 𝑐2 FA0 𝑦0 𝑥0 𝑧0 𝑐0 0 𝑦1 𝑥1 Cycle 2 Full adder adds 𝑦0 and 𝑥0. FA0…

**Figure 6.** Figure 6: Behavioural depiction of implemented bit-serial adder (left) and ripple-carry adder (right). The adders are processing addends 𝑥 and 𝑦, to yield sum 𝑧 and carry bits 𝑐. Subscripts represent bit indices. adder circuit reduces the MTJ writes in an addition from 16 to 7. …

**Figure 8.** Figure 8: Data organization of multiplicand, multiplier and partial product terms. 1 1 1 0 1 0 1 1 1 Read/write port 0 1 1 0 1 0 1 1 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 0 0 1 0 (1) Partial Product Write Stage Padded zeroes 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 …

**Figure 9.** Figure 9: Write and alignment stages of partial product accumulation. The partial products are shaded in grey. the resources used (CMOS logic and racetracks) and number of cycles for partial product generation scale linearly with operand bit-width. By optimizing the area-perfor…

**Figure 11.** Figure 11: Implementation of shift-based multiplier of DWMAcc to the multiplicand only to yield the same binary sequence shifted several positions. With characteristics of a shift register, racetrack memory is especially suitable for accelerating shift operations. Chen et al. […

**Figure 10.** Figure 10: Write and alignment stages of partial product accumulation. The partial products are shaded in grey. as inputs to an adder tree, made of the proposed full adders in Section 3.1. The full adders accumulate the partial products in bit-serial fashion: the 𝑆 bit is transf…

**Figure 12.** Figure 12: Initial data organization for shift-based adder, and shift-and-add example. • Due to the padded zeroes, the approach of DWMAcc does not support sign extension and is appropriate only for unsigned numbers. • When the number of padded zeroes is equal to the data bit-wid…

**Figure 13.** Figure 13: depicts the access mechanism of our shift-based multiplier design for the example considered. The figure also shows the correct alignment of terms for accumulation and the multiplier’s progress in different cycles. In order to execute shift-and-add, the four activatio…

**Figure 15.** Figure 15: Control circuitry implementing write-shift transformation. energy is an order of magnitude higher. Hence, we propose a novel energy optimization that converts write operations in RM-based arithmetic circuits to shift operations for greater efficiency. As the MTJs in …

**Figure 17.** Figure 17: Access phase and position-reset phase of four racetracks in an MU. The gold block represents an access port which reads/writes the four bits aligned with it [PITH_FULL_IMAGE:figures/full_fig_p010_17.png]

**Figure 18.** Figure 18: Memory organization of accelerator, as simulated in NVSim. The dark red blocks represent our proposed multiplier circuitry, whereas the dark blue blocks are adder unit blocks [PITH_FULL_IMAGE:figures/full_fig_p011_18.png]

**Figure 19.** Figure 19: An activation mat consisting of four subarrays and two bit-serial adder units. from SAR2 and SAR3 . The adder units then write the output sum to one of the four subarrays. Both adder units have write access to all four subarrays. Alternatively, the adder units can rec…

**Figure 21.** Figure 21: Data placement of activations and weights within subarrays. two subarrays in a mat group, where 𝐼(𝑟, 𝑐) represents the activation at the 𝑟 𝑡ℎ row and 𝑐 𝑡ℎ column of the input channel. The figure also depicts the first filter channel stored in a weight mat of the same …

**Figure 22.** Figure 22: Accumulation between mat groups using the banklevel adder tree. The top half refers to the first accumulation pass, followed by that in the bottom half. Each mat group has two stored channels; the bolded one is accessed. than subarray accesses. Secondly, unlike Booth…

**Figure 23.** Figure 23: Energy per bit (pJ) of Booth multiplier at varying bit-widths, with and without the write-shift energy optimization. per bit of the shift-based multiplier across different bitwidths as well as different shift distances. Lastly, we present and compare the latencies o…

**Figure 24.** Figure 24: Energy per bit (pJ) of the proposed shift-based multiplier. activations of 𝑁𝑏 bits and adding them together, as the shifting and accumulation process occur together [PITH_FULL_IMAGE:figures/full_fig_p016_24.png]

**Figure 26.** Figure 26: Latencies in cycles of different multipliers performing a multiply-and-accumulate (MAC) operation. area cost is minimal and does not vary significantly with the parameters. Lastly, we evaluate the latencies of different multipliers in performing a MAC operation. The …

**Figure 27.** Figure 27: Comparison of total energy for LeNet-5 and ResNet20 without the write-shift optimization to the energy after write-shift transformation is applied. 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0 20 40 60 80 100 120 140 160 16-bit 8-bit 4-bit Latency (MCycles) Energy ( …

**Figure 28.** Figure 28: and [PITH_FULL_IMAGE:figures/full_fig_p018_28.png]

**Figure 29.** Figure 29: Total energy, latency, and accuracy of a ResNet-20 inference on our RM-based accelerator. the model accuracies to explore the trade-off between overheads and accuracy during prediction. We consider only bit-widths between 4 to 16 bits, which has been found in literat…

**Figure 30.** Figure 30: Total energy, latency, and accuracy of a LeNet-5 inference on our RM-based accelerator (fixed point and shiftbased). 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 Fixed Point ±15 ±7 ±3 Fixed Point ±15 ±7 ±3 Fixed Point ±15 ±7 ±3 16-bit 8-bit 4-bit Latency (MCycles) E…

**Figure 31.** Figure 31: Total energy, latency, and accuracy of a ResNet-20 inference on our RM-based accelerator (fixed point and shiftbased). In both models, the shift distance has significant impact on the accuracy of inference. Hence, the required shift distance for accurate inference ca…

**Figure 32.** Figure 32: DRAM accesses per frame (image) for 8-bit fixed point VGG-16 by batch size. As elaborated in Section 5.2.2, we map VGG-16 to a 16- bank accelerator with 32 MB capacity. We perform inferences using power-of-two batch sizes from 1 (no batching) to 64 [PITH_FULL_IMAGE:…

**Figure 34.** Figure 34: presents the energy efficiency of both the fixed point and shift-based models at varying batch sizes. In this estimate, we include computation energy and dynamic access energy on-chip, as well as energy consumed for DRAM accesses estimated at 70 pJ/bit [17, 35]. From …

**Figure 35.** Figure 35: Energy efficiency, performance, and accuracy of the three CNN models across different configurations [PITH_FULL_IMAGE:figures/full_fig_p022_35.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

74 extracted references · 59 canonical work pages

[1]

Nullhop: A flexible convolutional neural network accelerator based on sparse representations of feature maps

Aimar, A., Mostafa, H., Calabrese, E., Rios-Navarro, A., Tapiador- Morales,R.,Lungu,I.A.,Milde,M.B.,Corradi,F.,Linares-Barranco, A., Liu, S.C., et al., 2018. Nullhop: A flexible convolutional neural network accelerator based on sparse representations of feature maps. IEEE transactions on neural networks and learning systems 30, 644– 656

work page 2018
[2]

A signed binary multiplication technique

Booth, A.D., 1951. A signed binary multiplication technique. The Quarterly Journal of Mechanics and Applied Mathematics 4, 236–

work page 1951
[3]

Skyrmion logic system for large- scale reversible computation

Chauwin, M., Hu, X., Garcia-Sanchez, F., Betrabet, N., Paler, A., Moutafis, C., Friedman, J.S., 2019. Skyrmion logic system for large- scale reversible computation. Physical Review Applied 12, 064053

work page 2019
[4]

Flinkcl: An opencl- based in-memory computing architecture on heterogeneous cpu-gpu clusters for big data

Chen, C., Li, K., Ouyang, A., Li, K., 2018a. Flinkcl: An opencl- based in-memory computing architecture on heterogeneous cpu-gpu clusters for big data. IEEE Transactions on Computers 67, 1765– 1779

work page
[5]

IEEE Transactions on Systems, Man, and Cybernetics: Systems 47, 2740–2753

Chen,C.,Li,K.,Ouyang,A.,Tang,Z.,Li,K.,2017a.Gpu-accelerated parallel hierarchical extreme learning machine on flink for big data. IEEE Transactions on Systems, Man, and Cybernetics: Systems 47, 2740–2753

work page
[6]

Gflink: An in- memory computing architecture on heterogeneous cpu-gpu clusters Choong et

Chen, C., Li, K., Ouyang, A., Zeng, Z., Li, K., 2018b. Gflink: An in- memory computing architecture on heterogeneous cpu-gpu clusters Choong et. al.: Preprint submitted to Elsevier Page 23 of 25 Co-exploration of racetrack memory based CNN inference for big data. IEEE Transactions on Parallel and Distributed Systems 29, 1275–1288

work page
[7]

Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

Chen, Y.H., Krishna, T., Emer, J.S., Sze, V., 2017b. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE Journal of Solid-State Circuits 52, 127–138. doi:10.1109/JSSC.2016.2616357

arXiv 2016
[8]

Dwmacc: Accelerating shift-based cnns with domain wall memories

Chen, Z., Deng, Q., Xiao, N., Pruhs, K., Zhang, Y., 2019. Dwmacc: Accelerating shift-based cnns with domain wall memories. ACM Trans. Embed. Comput. Syst. 18. URL:https://doi-org.libproxy1. nus.edu.sg/10.1145/3358199, doi:10.1145/3358199

work page doi:10.1145/3358199 2019

Show all 74 references

[9]

The mnist database of handwritten digit images for machine learning research

Deng, L., 2012. The mnist database of handwritten digit images for machine learning research. IEEE Signal Processing Magazine 29, 141–142

2012
[10]

Quantized deep neural networks for energy efficient hardware-based inference, in:201823rdAsiaandSouthPacificDesignAutomationConference (ASP-DAC), pp

Ding, R., Liu, Z., Blanton, R.D.S., Marculescu, D., 2018. Quantized deep neural networks for energy efficient hardware-based inference, in:201823rdAsiaandSouthPacificDesignAutomationConference (ASP-DAC), pp. 1–8. doi:10.1109/ASPDAC.2018.8297274

2018
[11]

Nvsim: A circuit- level performance, energy, and area model for emerging nonvolatile memory.IEEETransactionsonComputer-AidedDesignofIntegrated Circuits and Systems 31, 994–1007

Dong, X., Xu, C., Xie, Y., Jouppi, N.P., 2012. Nvsim: A circuit- level performance, energy, and area model for emerging nonvolatile memory.IEEETransactionsonComputer-AidedDesignofIntegrated Circuits and Systems 31, 994–1007. doi:10.1109/TCAD.2012.2185930

2012
[12]

Neural cache: Bit-serial in-cache acceleration of deep neural networks, in: 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), pp

Eckert,C.,Wang,X.,Wang,J.,Subramaniyan,A.,Iyer,R.,Sylvester, D., Blaaauw, D., Das, R., 2018. Neural cache: Bit-serial in-cache acceleration of deep neural networks, in: 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), pp. 383–396. doi:10.1109/...

2018
[13]

Deepcompression:Compressing deepneuralnetworkswithpruning,trainedquantizationandhuffman coding

Han,S.,Mao,H.,Dally,W.J.,2016. Deepcompression:Compressing deepneuralnetworkswithpruning,trainedquantizationandhuffman coding. arXiv:1510.00149

2016 arXiv
[14]

Deep residual learning for image recognition, in: 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pp

He, K., Zhang, X., Ren, S., Sun, J., 2016. Deep residual learning for image recognition, in: 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pp. 770–778. doi:10.1109/CVPR. 2016.90

2016 doi
[15]

Hegde, K., Yu, J., Agrawal, R., Yan, M., Pellauer, M., Fletcher, C.,
[16]

Mobilenets: Effi- cient convolutional neural networks for mobile vision applications

Howard, A.G., Zhu, M., Chen, B., Kalenichenko, D., Wang, W., Weyand, T., Andreetto, M., Adam, H., 2017. Mobilenets: Effi- cient convolutional neural networks for mobile vision applications. CoRR abs/1704.04861. URL: http://arxiv.org/abs/1704.04861, arXiv:1704.04861

2017 arXiv
[17]

Essa: An energy-aware bit-serial streaming deep convolutional neu- ral network accelerator

Hsu, L.C., Chiu, C.T., Lin, K.T., Chou, H.H., Pu, Y.Y., 2020. Essa: An energy-aware bit-serial streaming deep convolutional neu- ral network accelerator. Journal of Systems Architecture 111, 101831. URL: https://www.sciencedirect.com/science/article/ pii/S1383762120301235, doi...

2020 doi
[18]

Exploring main memory designbasedonracetrackmemorytechnology,in:2016International Great Lakes Symposium on VLSI (GLSVLSI), pp

Hu, Q., Sun, G., Shu, J., Zhang, C., 2016. Exploring main memory designbasedonracetrackmemorytechnology,in:2016International Great Lakes Symposium on VLSI (GLSVLSI), pp. 397–402. doi:10. 1145/2902961.2902967

2016
[19]

Batch normalization: Accelerat- ing deep network training by reducing internal covariate shift

Ioffe, S., Szegedy, C., 2015. Batch normalization: Accelerat- ing deep network training by reducing internal covariate shift. CoRR abs/1502.03167. URL: http://arxiv.org/abs/1502.03167, arXiv:1502.03167

2015 arXiv
[20]

Quantizationandtrainingofneu- ral networks for efficient integer-arithmetic-only inference, in: 2018 IEEE/CVFConferenceonComputerVisionandPatternRecognition, pp

Jacob, B., Kligys, S., Chen, B., Zhu, M., Tang, M., Howard, A., Adam,H.,Kalenichenko,D.,2018. Quantizationandtrainingofneu- ral networks for efficient integer-arithmetic-only inference, in: 2018 IEEE/CVFConferenceonComputerVisionandPatternRecognition, pp. 2704–2713. doi:10.110...

2018
[21]

Accelerator-awarepruningforconvolutionalneural networks

Kang,H.J.,2020. Accelerator-awarepruningforconvolutionalneural networks. IEEE Transactions on Circuits and Systems for Video Technology 30, 2093–2103. doi:10.1109/TCSVT.2019.2911674

2020
[22]

skyrmion, in: 2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA), IEEE

Kang,W.,Chen,X.,Zhu,D.,Zhang,X.,Zhou,Y.,Qiu,K.,Zhang,Y., Zhao,W.,2018.Acomparativestudyonracetrackmemories:Domain wall vs. skyrmion, in: 2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA), IEEE. pp. 7–12

2018
[23]

Compact modeling and evaluation of magnetic skyrmion- basedracetrackmemory

Kang, W., Zheng, C., Huang, Y., Zhang, X., Lv, W., Zhou, Y., Zhao, W., 2017. Compact modeling and evaluation of magnetic skyrmion- basedracetrackmemory. IEEETransactionsonElectronDevices64, 1060–1068

2017
[24]

Exploiting retraining-basedmixed-precisionquantizationforlow-costdnnaccel- erator design

Kim, N., Shin, D., Choi, W., Kim, G., Park, J., 2020. Exploiting retraining-basedmixed-precisionquantizationforlow-costdnnaccel- erator design. IEEE Transactions on Neural Networks and Learning Systems 32, 2925–2938

2020
[25]

Heterogeneous dataflow accelerators for multi-dnn work- loads,in:2021IEEEInternationalSymposiumonHigh-Performance Computer Architecture (HPCA), IEEE

Kwon, H., Lai, L., Pellauer, M., Krishna, T., Chen, Y.H., Chandra, V., 2021. Heterogeneous dataflow accelerators for multi-dnn work- loads,in:2021IEEEInternationalSymposiumonHigh-Performance Computer Architecture (HPCA), IEEE. pp. 71–83

2021
[26]

Gradient-based learning applied to document recognition

Lecun, Y., Bottou, L., Bengio, Y., Haffner, P., 1998. Gradient-based learning applied to document recognition. Proceedings of the IEEE 86, 2278–2324. doi:10.1109/5.726791

1998 doi
[27]

Lognet:Energy-efficientneuralnetworksusinglogarithmiccomputa- tion, in: 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp

Lee, E.H., Miyashita, D., Chai, E., Murmann, B., Wong, S.S., 2017. Lognet:Energy-efficientneuralnetworksusinglogarithmiccomputa- tion, in: 2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 5900–5904. doi: 10.1109/ ICASSP.2017.7953288

2017
[28]

45nm low power cmos logic compatible embedded stt mram utilizing a reverse-connection 1t/1mtj cell, in: 2009 IEEE International Electron Devices Meeting (IEDM), pp

Lin, C., Kang, S., Wang, Y., Lee, K., Zhu, X., Chen, W., Li, X., Hsu, W., Kao, Y., Liu, M., Chen, W., Lin, Y., Nowak, M., Yu, N., Tran, L., 2009. 45nm low power cmos logic compatible embedded stt mram utilizing a reverse-connection 1t/1mtj cell, in: 2009 IEEE International Ele...

2009
[29]

Liu, B., Gu, S., Chen, M., Kang, W., Hu, J., Zhuge, Q., Sha, E.H.M.,
[30]

Skyrmion devices for memory and logic applications

Luo, S., You, L., 2021. Skyrmion devices for memory and logic applications. APL Materials 9, 050901

2021
[31]

A novel two- stage modular multiplier based on racetrack memory for asymmet- ric cryptography, in: 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), IEEE

Luo, T., He, B., Zhang, W., Maskell, D.L., 2017. A novel two- stage modular multiplier based on racetrack memory for asymmet- ric cryptography, in: 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), IEEE. pp. 276–282

2017
[32]

An fpga-based hardware emulator for neuromorphic chip with rram

Luo,T.,Wang,X.,Qu,C.,Lee,M.K.F.,Tang,W.T.,Wong,W.F.,Goh, R.S.M., 2018. An fpga-based hardware emulator for neuromorphic chip with rram. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 438–450

2018
[33]

Energy efficient in-memory integer multiplication based on racetrack mem- ory, in: 2020 IEEE 40th International Conference on Distributed Computing Systems (ICDCS), IEEE

Luo, T., Zhang, W., He, B., Liu, C., Maskell, D., 2020. Energy efficient in-memory integer multiplication based on racetrack mem- ory, in: 2020 IEEE 40th International Conference on Distributed Computing Systems (ICDCS), IEEE. pp. 1409–1414

2020
[34]

A racetrack memory based in-memory booth multiplier for cryptography application, in: 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE

Luo, T., Zhang, W., He, B., Maskell, D., 2016. A racetrack memory based in-memory booth multiplier for cryptography application, in: 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE. pp. 286–291

2016
[35]

Towards energy-proportional datacenter memory with mobile dram, in: 2012 39th Annual International Sym- posium on Computer Architecture (ISCA), pp

Malladi,K.T.,Nothaft,F.A.,Periyathambi,K.,Lee,B.C.,Kozyrakis, C., Horowitz, M., 2012. Towards energy-proportional datacenter memory with mobile dram, in: 2012 39th Annual International Sym- posium on Computer Architecture (ISCA), pp. 37–48. doi:10.1109/ ISCA.2012.6237004

2012
[36]

Exploration of gpgpu register file architecture using domain-wall-shift-write based racetrack memory, in: Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE, pp

Mao, M., Wen, W., Zhang, Y., Chen, Y., Li, H., 2014. Exploration of gpgpu register file architecture using domain-wall-shift-write based racetrack memory, in: Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE, pp. 1–6

2014
[37]

An energy- efficient gpgpu register file architecture using racetrack memory

Mao, M., Wen, W., Zhang, Y., Chen, Y., Li, H., 2017. An energy- efficient gpgpu register file architecture using racetrack memory. IEEE Transactions on Computers 66, 1478–1490

2017
[38]

Applied Physics Express 1, 091301

Matsunaga, S., Hayakawa, J., Ikeda, S., Miura, K., Hasegawa, H., Endoh,T.,Ohno,H.,Hanyu,T.,2008.Fabricationofanonvolatilefull adder based on logic-in-memory architecture using magnetic tunnel junctions. Applied Physics Express 1, 091301. Choong et. al.: Preprint submitted to E...

2008
[39]

Zigzag: Enlarging joint architecture-mapping design space explo- ration for dnn accelerators

Mei, L., Houshmand, P., Jain, V., Giraldo, S., Verhelst, M., 2021. Zigzag: Enlarging joint architecture-mapping design space explo- ration for dnn accelerators. IEEE Transactions on Computers 70, 1160–1174

2021
[40]

A spintronics full adder for magnetic cpu

Meng, H., Wang, J., Wang, J.P., 2005. A spintronics full adder for magnetic cpu. Electron Device Letters, IEEE 26, 360–362

2005
[41]

Anenergy-efficientprecision-scalable convnetprocessorin40-nmcmos.IEEEJournalofsolid-stateCircuits 52, 903–914

Moons,B.,Verhelst,M.,2016. Anenergy-efficientprecision-scalable convnetprocessorin40-nmcmos.IEEEJournalofsolid-stateCircuits 52, 903–914

2016
[42]

Magneticdomain-wall racetrack memory

Parkin,S.S.P.,Hayashi,M.,Thomas,L.,2008. Magneticdomain-wall racetrack memory. Science 320, 190–194. URL:https://science. sciencemag.org/content/320/5873/190, doi:10.1126/science.1145799

2008 doi
[43]

Pytorch: An imper- ative style, high-performance deep learning library, in: Advances in Neural Information Processing Systems 32

Paszke, A., Gross, S., Massa, F., Lerer, A., Bradbury, J., Chanan, G., Killeen,T.,Lin,Z.,Gimelshein,N.,Antiga,L.,Desmaison,A.,Kopf, A., Yang, E., DeVito, Z., Raison, M., Tejani, A., Chilamkurthy, S., Steiner, B., Fang, L., Bai, J., Chintala, S., 2019. Pytorch: An imper- ative ...

2019
[44]

Parallelcom- putation in the racetrack memory

Riente,F.,Turvani,G.,Vacca,M.,Graziano,M.,2021. Parallelcom- putation in the racetrack memory. IEEE Transactions on Emerging Topics in Computing

2021
[45]

ImageNet Large Scale Visual Recognition Challenge

Russakovsky, O., Deng, J., Su, H., Krause, J., Satheesh, S., Ma, S., Huang, Z., Karpathy, A., Khosla, A., Bernstein, M., Berg, A.C., Fei- Fei, L., 2015. ImageNet Large Scale Visual Recognition Challenge. International Journal of Computer Vision (IJCV) 115, 211–252. doi:10.1007...

2015 doi
[46]

Sharma, H., Park, J., Suda, N., Lai, L., Chau, B., Chandra, V., Esmaeilzadeh, H., 2018. Bit fusion: Bit-level dynamically com- posable architecture for accelerating deep neural network, in: 2018 ACM/IEEE 45th Annual International Symposium on Computer Ar- chitecture (ISCA), IE...

2018
[47]

45nm freepdk library URL: https://si2.org/open-cell-library/

Silicon Integration Initiative, I., 2016. 45nm freepdk library URL: https://si2.org/open-cell-library/

2016
[48]

Very deep convolutional net- works for large-scale image recognition, in: Bengio, Y., LeCun, Y

Simonyan, K., Zisserman, A., 2015. Very deep convolutional net- works for large-scale image recognition, in: Bengio, Y., LeCun, Y. (Eds.), 3rd International Conference on Learning Representations, ICLR 2015, San Diego, CA, USA, May 7-9, 2015, Conference Track Proceedings. URL:...

2015 arXiv
[49]

Stt-ram buffer design for precision-tunable general-purpose neural network accelerator

Song, L., Wang, Y., Han, Y., Li, H., Cheng, Y., Li, X., 2017. Stt-ram buffer design for precision-tunable general-purpose neural network accelerator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, 1285–1296

2017
[50]

Cross-layer racetrack memory design for ultra high density and low power consumption, in: Design AutomationConference(DAC),201350thACM/EDAC/IEEE,pp.1– 6

Sun, Z., Wu, W., Li, H., 2013. Cross-layer racetrack memory design for ultra high density and low power consumption, in: Design AutomationConference(DAC),201350thACM/EDAC/IEEE,pp.1– 6

2013
[51]

Magnetic adder based on racetrack memory

Trinh, H.P., Zhao, W., Klein, J.O., Zhang, Y., Ravelsona, D., Chap- pert, C., 2013. Magnetic adder based on racetrack memory. IEEE Transactions on Circuits and Systems I: Regular Papers 60, 1469–

2013
[52]

Stag: Spintronic-tape architecture for gpgpu cache hierarchies, in: Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on, pp

Venkatesan, R., Ramasubramanian, S.G., Venkataramani, S., Roy, K., Raghunathan, A., 2014. Stag: Spintronic-tape architecture for gpgpu cache hierarchies, in: Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on, pp. 253–264

2014
[53]

Dwm- tapestri-an energy efficient all-spin cache using domain wall shift based writes, in: Proceedings of the Conference on Design, Automa- tion and Test in Europe, EDA Consortium

Venkatesan, R., Sharad, M., Roy, K., Raghunathan, A., 2013. Dwm- tapestri-an energy efficient all-spin cache using domain wall shift based writes, in: Proceedings of the Conference on Design, Automa- tion and Test in Europe, EDA Consortium. pp. 1825–1830

2013
[54]

Ultra-dense ring-shaped racetrack memory cache design

Wang, G., Zhang, Y., Zhang, B., Wu, B., Nan, J., Zhang, X., Zhang, Z., Klein, J.O., Ravelosona, D., Wang, Z., et al., 2018. Ultra-dense ring-shaped racetrack memory cache design. IEEE Transactions on Circuits and Systems I: Regular Papers , 1–11

2018
[55]

An automatic- addressingarchitecturewithfullyserializedaccessinracetrackmem- ory for energy-efficient cnns

Wang, J., Liu, J., Wang, D., An, J., Fan, X., 2020. An automatic- addressingarchitecturewithfullyserializedaccessinracetrackmem- ory for energy-efficient cnns. IEEE Transactions on Computers

2020
[56]

Dw-aes: A domain- wall nanowire-based aes for high throughput and energy-efficient data encryption in non-volatile memory

Wang, Y., Ni, L., Chang, C.H., Yu, H., 2016. Dw-aes: A domain- wall nanowire-based aes for high throughput and energy-efficient data encryption in non-volatile memory. IEEE Transactions on Information Forensics and Security 11, 2426–2440

2016
[57]

Energy efficient in- memory aes encryption based on nonvolatile domain-wall nanowire, in:Design,AutomationandTestinEuropeConferenceandExhibition (DATE), 2014, IEEE

Wang, Y., Yu, H., Sylvester, D., Kong, P., 2014. Energy efficient in- memory aes encryption based on nonvolatile domain-wall nanowire, in:Design,AutomationandTestinEuropeConferenceandExhibition (DATE), 2014, IEEE. pp. 1–4

2014
[58]

Multilane racetrack caches: Improving efficiency through compression and independent shifting, in: Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific, IEEE

Xu, H., Li, Y., Melhem, R., Jones, A.K., 2015. Multilane racetrack caches: Improving efficiency through compression and independent shifting, in: Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific, IEEE. pp. 417–422

2015
[59]

Designing energy-efficient convolutional neural networks using energy-aware pruning, in: 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pp

Yang, T.J., Chen, Y.H., Sze, V., 2017. Designing energy-efficient convolutional neural networks using energy-aware pruning, in: 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), pp. 6071–6079. doi:10.1109/CVPR.2017.643

2017 doi
[60]

Yu, H., Wang, Y., Chen, S., Fei, W., Weng, C., Zhao, J., Wei, Z.,
[61]

Energy-efficient nonvolatile reconfigurable logic using spin hall effect-based lookup tables

Zand, R., Roohi, A., Fan, D., DeMara, R.F., 2017. Energy-efficient nonvolatile reconfigurable logic using spin hall effect-based lookup tables. IEEE Transactions on Nanotechnology 16, 32–43

2017
[62]

Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power, in: The 20th Asia and South Pacific Design Automation Conference, pp

Zhang, C., Sun, G., Zhang, W., Mi, F., Li, H., Zhao, W., 2015a. Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power, in: The 20th Asia and South Pacific Design Automation Conference, pp. 100–105. doi: 10.1109/ASPDAC.2015. 7058988

doi
[63]

In-memory computation of a machine-learning classifier in a standard 6t sram array

Zhang, J., Wang, Z., Verma, N., 2017. In-memory computation of a machine-learning classifier in a standard 6t sram array. IEEE Journal of Solid-State Circuits 52, 915–924. doi:10.1109/JSSC.2016.2642198

2017
[64]

Magnetic skyrmion logic gates: conversion, duplication and merging of skyrmions

Zhang, X., Ezawa, M., Zhou, Y., 2015b. Magnetic skyrmion logic gates: conversion, duplication and merging of skyrmions. Scientific reports 5, 1–8
[65]

Perpendicular-magnetic-anisotropy cofeb racetrack mem- ory

Zhang, Y., Zhao, W., Ravelosona, D., Klein, J.O., Kim, J., Chappert, C., 2012. Perpendicular-magnetic-anisotropy cofeb racetrack mem- ory. Journal of Applied Physics 111, 093925

2012
[66]

Zhao, W., Romdhane, N.B., Zhang, Y., Klein, J.O., Ravelosona, D.,
[67]

Incremen- tal network quantization: Towards lossless cnns with low-precision weights

Zhou, A., Yao, A., Guo, Y., Xu, L., Chen, Y., 2017. Incremen- tal network quantization: Towards lossless cnns with low-precision weights. CoRR abs/1702.03044. URL: http://arxiv.org/abs/1702. 03044, arXiv:1702.03044

2017 arXiv
[68]

An efficient hardware accelerator for structured sparse convolutional neural networks on fpgas

Zhu, C., Huang, K., Yang, S., Zhu, Z., Zhang, H., Shen, H., 2020. An efficient hardware accelerator for structured sparse convolutional neural networks on fpgas. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, 1953–1965. Choong et. al.: Preprint submitted ...

2020
[240]

URL: https://doi.org/10.1093/qjmam/4.2.236, doi:10.1093/ qjmam/4.2.236

doi
[1477]

doi:10.1109/TCSI.2012.2220507

2012
[2013]

Racetrack memory based reconfigurable computing, in: Faible Tension Faible Consommation (FTFC), 2013 IEEE, IEEE. pp. 1–4

2013
[2014]

Energyefficientin-memorymachinelearningfordataintensive image-processingbynon-volatiledomain-wallmemory,in:201419th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 191–196. doi:10.1109/ASPDAC.2014.6742888

2014
[2017]

An efficient racetrack memory-based processing-in-memory architecture for convolutional neural networks, in: 2017 IEEE In- ternational Symposium on Parallel and Distributed Processing with Applicationsand2017IEEEInternationalConferenceonUbiquitous ComputingandCommunications(IS...

2017
[2018]

Ucnn:Exploitingcomputationalreuseindeepneuralnetworks viaweightrepetition,in:2018ACM/IEEE45thAnnualInternational SymposiumonComputerArchitecture(ISCA),pp.674–687. doi: 10. 1109/ISCA.2018.00062

2018

Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.

[1] [1]

Nullhop: A flexible convolutional neural network accelerator based on sparse representations of feature maps

Aimar, A., Mostafa, H., Calabrese, E., Rios-Navarro, A., Tapiador- Morales,R.,Lungu,I.A.,Milde,M.B.,Corradi,F.,Linares-Barranco, A., Liu, S.C., et al., 2018. Nullhop: A flexible convolutional neural network accelerator based on sparse representations of feature maps. IEEE transactions on neural networks and learning systems 30, 644– 656

work page 2018

[2] [2]

A signed binary multiplication technique

Booth, A.D., 1951. A signed binary multiplication technique. The Quarterly Journal of Mechanics and Applied Mathematics 4, 236–

work page 1951

[3] [3]

Skyrmion logic system for large- scale reversible computation

Chauwin, M., Hu, X., Garcia-Sanchez, F., Betrabet, N., Paler, A., Moutafis, C., Friedman, J.S., 2019. Skyrmion logic system for large- scale reversible computation. Physical Review Applied 12, 064053

work page 2019

[4] [4]

Flinkcl: An opencl- based in-memory computing architecture on heterogeneous cpu-gpu clusters for big data

Chen, C., Li, K., Ouyang, A., Li, K., 2018a. Flinkcl: An opencl- based in-memory computing architecture on heterogeneous cpu-gpu clusters for big data. IEEE Transactions on Computers 67, 1765– 1779

work page

[5] [5]

IEEE Transactions on Systems, Man, and Cybernetics: Systems 47, 2740–2753

Chen,C.,Li,K.,Ouyang,A.,Tang,Z.,Li,K.,2017a.Gpu-accelerated parallel hierarchical extreme learning machine on flink for big data. IEEE Transactions on Systems, Man, and Cybernetics: Systems 47, 2740–2753

work page

[6] [6]

Gflink: An in- memory computing architecture on heterogeneous cpu-gpu clusters Choong et

Chen, C., Li, K., Ouyang, A., Zeng, Z., Li, K., 2018b. Gflink: An in- memory computing architecture on heterogeneous cpu-gpu clusters Choong et. al.: Preprint submitted to Elsevier Page 23 of 25 Co-exploration of racetrack memory based CNN inference for big data. IEEE Transactions on Parallel and Distributed Systems 29, 1275–1288

work page

[7] [7]

Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

Chen, Y.H., Krishna, T., Emer, J.S., Sze, V., 2017b. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE Journal of Solid-State Circuits 52, 127–138. doi:10.1109/JSSC.2016.2616357

arXiv 2016

[8] [8]

Dwmacc: Accelerating shift-based cnns with domain wall memories

Chen, Z., Deng, Q., Xiao, N., Pruhs, K., Zhang, Y., 2019. Dwmacc: Accelerating shift-based cnns with domain wall memories. ACM Trans. Embed. Comput. Syst. 18. URL:https://doi-org.libproxy1. nus.edu.sg/10.1145/3358199, doi:10.1145/3358199

work page doi:10.1145/3358199 2019