An automated redaction flow that customizes the eFPGA fabric per hidden module cluster cuts area and power overhead by up to 3.3x and raises fabric utilization by up to 4x.
Benchmarking at the frontier of hardware security: Lessons from logic locking,
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ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
An automated redaction flow that customizes the eFPGA fabric per hidden module cluster cuts area and power overhead by up to 3.3x and raises fabric utilization by up to 4x.