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REVIEW 4 major objections 6 minor 45 references

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction

T0 review · 4 major / 6 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read ARIANNA claims that tailoring the embedded-FPGA fabric to each redacted module cluster, instead of using one fixed fabric, cuts hardware redaction overhead by up to 3.3x and raises fabric utilization by 4x.

desk verdict Solid empirical extension of ALICE that adds per-cluster fabric customization and cuts overheads on benchmarks, but the tile-count proxy and unenforced security filter keep the 'automatic' claim from being fully true. read the letter →

arxiv 2506.00857 v1 pith:6TB66XWI submitted 2025-06-01 cs.CR

Luca Collini , Jitendra Bhandari , Chiara Muscari Tomajoli , Abdul Khader Thalakkattu Moosa , Benjamin Tan , Xifan Tang , Pierre-Emmanuel Gaillardon , Ramesh Karri
show 1 more author
Christian Pilato
This is my paper
classification cs.CR
keywords eFPGAredactionhardwareIPprotectionfabriccustomizationdesignspaceexplorationSATattackresilienceRTLmoduleclusteringlogicobfuscation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

ARIANNA is a design flow that makes eFPGA-based IP redaction cheaper by treating the embedded FPGA fabric itself as something to customize. The paper's central claim is that choosing a bespoke fabric configuration for each cluster of redacted RTL modules, rather than reusing one fixed fabric for every design, cuts area, power, and timing overhead by up to 3.3x and raises fabric utilization by up to 4x on the tested benchmarks. To reach that result, the flow first filters and clusters candidate modules, then uses two greedy heuristics to search the fabric parameter space ($N$ BLEs per configurable logic block and $K$ LUT inputs), and finally selects non-overlapping eFPGAs by a utilization-based score. A one-time security pre-screen removes fabric configurations that a SAT-based attack can break at the intended eFPGA size. If the claim holds, designers can protect more logic behind redaction at a cost that is closer to logic locking.

What carries the argument

The central mechanism is the bespoke eFPGA fabric, an embedded FPGA whose configurable logic blocks are parameterized by $N$, the number of basic logic elements per block, and $K$, the number of LUT inputs, with the CLB input count set to $I = K(N+1)/2$. The $NK$ and $KN$ heuristics carry the search: starting from the largest allowed $N$ and $K$, each heuristic decreases one parameter until the OpenFPGA tile count increases, then fixes it and decreases the other, thereby exploring only the cheapest tile-minimal configurations. The selection phase then ranks solutions by the score $T_f = \frac{\text{MaxIOUtil}-\text{IOUtil}_f}{\text{MaxIOUtil}} + \frac{\text{MaxCLBUtil}-\text{CLBUtil}_f}{\text{MaxCLBUtil}}$, which balances I/O and CLB utilization and doubles as a proxy for security because underutilized fabrics leak more information to SAT-style attacks.

What would settle it

Take a previously unseen benchmark, enumerate every admissible $(N,K)$ pair for each cluster, and compare the post-synthesis area of the $NK$- and $KN$-chosen fabrics to the exhaustive minimum. If the heuristic choices are consistently more than a few percent above the minimum, or if the 22-out-of-291 failure rate grows substantially, the claim that tile count is a sufficient optimization proxy fails. A second check is to apply the flow to a design with irregular routing congestion, where tile count and area are known to diverge.

Watch

Extended reading notes

Core claim

The paper's core discovery is that the fabric configuration of an eFPGA used for redaction should be a design variable rather than a fixed constant. For each cluster of modules to hide, ARIANNA runs the open-source FPGA toolchain on candidate $(N,K)$ pairs and keeps the smallest tile grid that still implements the cluster, with two greedy heuristics ($NK$ and $KN$) that shrink one parameter at a time until the tile count rises. In the full flow, candidate fabrics are scored by I/O and CLB utilization, and a branch-and-bound selection step chooses a set of eFPGAs whose module instances do not overlap. Compared with the fixed 4-4 fabric of the prior ALICE flow, the tailored fabrics reduce hardware overhead by up to 3.3x and increase fabric utilization by up to 4x, while the heuristics stay an order of magnitude faster than exhaustive exploration on most benchmarks.

Load-bearing premise

The load-bearing assumption is that the fabric with the fewest tiles is also the one with the lowest post-synthesis area, power, and timing, and the paper itself shows this proxy can fail in 22 of 291 clusters where a larger-tile fabric had lower area.

Editorial extensions

If this is right

  • A designer can redact a larger set of modules, such as all eight DES3 S-boxes, while paying less area and power than the previous fixed-fabric flow, because the fabric is matched to what the cluster actually needs.
  • The secure-fabric pre-screen is reusable across designs, so the per-design cost of ARIANNA is limited to clustering, fabric exploration, and selection rather than re-evaluating attack resistance.
  • The $NK$ and $KN$ heuristics make fabric exploration tractable on designs where exhaustive enumeration of every $(N,K)$ pair would be too slow, with runtimes often over an order of magnitude below exhaustive search.
  • Higher CLB and I/O utilization means fewer wasted fabric resources and, according to the cited security studies, stronger resistance to SAT-based reverse engineering of the redacted logic.
  • Because non-minimum-tile fabrics can occasionally have lower synthesized area, the heuristics are an approximation, but in most of the 291 clusters tested they reproduce the exhaustive optimum.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper's direct claims, the tile-count proxy is the hinge of the method: the paper reports 22 of 291 clusters where a non-minimum-tile fabric had the minimum area, so a designer using ARIANNA on a congested or irregular design should spot-check the few largest-tile alternatives before committing.
  • If a stronger attack than the one used in the security pre-screen appears, the set of admissible fabrics shrinks and the smallest eFPGA sizes may no longer be safe, which would push the flow toward larger fabrics and higher overhead.
  • The authors hint that $KN$ tends to yield better synthesis results; a practical workflow could run $KN$ first and use $NK$ only as a cross-check, rather than treating the two symmetrically.
  • The scoring function could be extended beyond utilization to directly include post-synthesis area, power, and timing, which would remove the need to rely on tile count as the optimization proxy.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. ARIANNA is presented as an automatic flow for eFPGA-based IP redaction that jointly selects which RTL modules to redact and customizes the eFPGA fabric parameters (N, K) for each module cluster. The flow has four phases: secure fabric identification via an IcySAT attack evaluation, module filtering and clustering, a bespoke fabric design-space exploration with two greedy heuristics (NK and KN), and a final eFPGA selection step that ranks candidate solutions using a utilization-based score. The paper evaluates the two heuristics against an exhaustive search over 291 module clusters and evaluates the complete flow on seven benchmarks from CEP, IWLS05, OpenROAD, and Opencores, comparing against the ALICE baseline. The headline results are up to 3.3x lower area/power overhead and up to 4x higher fabric utilization than a one-fits-all fabric. The security analysis reports that, under a 48-hour IcySAT timeout, 4x4 fabrics are all breakable and only 6x6 fabrics are uniformly safe; nevertheless, several final solutions reported in the paper use 4x4 or 5x5 fabrics.

Significance. The paper addresses a real and timely problem: making eFPGA redaction practical by automating both module selection and fabric customization. Its strengths include a complete RTL-to-physical-design flow, a systematic exhaustive characterization of 291 clusters, two simple heuristics that reduce OpenFPGA runs by roughly an order of magnitude, and concrete synthesis and physical-design results on seven benchmarks against the ALICE baseline. The IcySAT-based secure-fabric study provides a reproducible security criterion, even though it is only one attack model. If the flow is corrected as suggested below, the contribution would be a useful step forward for the TODAES community. As written, however, the paper overclaims both the optimality of the automatic selection and the security of the final solutions, so the empirical results are not yet supported as properties of the flow.

major comments (4)
  1. [Section 5.5, Eq. (1)] The selection score in Eq. (1) is inverted with respect to the stated objective. As printed, T_f = (MaxIOUtil - IOUtil_f)/MaxIOUtil + (MaxCLBUtil - CLBUtil_f)/MaxCLBUtil, so fabrics with lower I/O and CLB utilization receive higher scores. This contradicts Section 6.3, which asserts that higher fabric utilization means less wasted resources and greater resilience, and it is inconsistent with the reported 4x utilization improvements. Since Algorithm 5 ranks all final solutions by T_f, either the formula should be T_f = IOUtil_f/MaxIOUtil + CLBUtil_f/MaxCLBUtil or the implementation must be documented; as written, the central utilization claim is not supported by the presented criterion.
  2. [Section 6.1 and Section 6.3, Table 4] The flow does not enforce its own security criterion. The IcySAT evaluation in Section 6.1 shows that all 4x4 fabrics are broken within the 48-hour timeout and that only 6x6 fabrics are uniformly safe, yet Table 4 lists many final ARIANNA solutions with 4x4 or 5x5 eFPGAs (e.g., DES3 cfg1, GCD, SHA256, SASC, USB_PHY). The paragraph following Figure 8 acknowledges that the 4x4 DES3 solution is orders of magnitude weaker to SAT attacks, and Section 6.3 suggests the designer add DisORC afterward. This makes the 'automatic' flow not security-preserving under the paper's own threat evaluation: either insecure sizes must be excluded before selection, or the cost of the additional countermeasure must be included in the reported overheads.
  3. [Section 5.4, Algorithms 3-4 and Section 6.2] The claimed overhead minimization rests on the unvalidated proxy that minimum tile count implies minimum post-synthesis area and power. Both heuristics stop at the first N or K value that changes the OpenFPGA tile count and never explore larger-grid configurations. Section 6.2 reports 22 of 291 clusters where the minimum-area fabric does not have the minimum tile count, and Table 2 shows that for GCD the NK and KN heuristics have average relative costs of 4.78x and 4.36x against the exhaustive best (std ~13.6). Because Algorithm 5 ranks candidates using the utilization score of Eq. (1), not synthesized area or power, the final chosen solution can be several times more expensive than the best available fabric, or worse than ALICE's fixed fabric. The headline improvements should be presented as empirical outcomes on these seven benchmarks, not as a property of the flow; a post-synthesis area/power check inside the selection loop, or a characterization of the heuristic loss, is needed to support the automatic-minimization claim.
  4. [Section 6.2] The heuristics were motivated by the exhaustive study performed on the same benchmarks used for validation: Section 6.2 states that the preliminary exhaustive analysis 'helped us formulate the proposed heuristics.' Validating the resulting heuristics on these same designs therefore risks optimistic results and does not measure generalization to new designs. A held-out benchmark or a parameter-sweep sensitivity analysis would make the efficiency claims more robust.
minor comments (6)
  1. [Algorithm 5] In Algorithm 5, line 9 initializes W to an empty set, so the loop 'foreach w in W' has no iterations and the returned solution set is empty; initialize W with the empty solution, e.g., W <- {empty}, to match the described behavior.
  2. [Algorithm 3] In Algorithm 3, the comment inside the first loop says 'Decrease K until size increases,' but the loop decreases N; the comment should refer to N.
  3. [Algorithms 3 and 4] The use of N and K for both the user-supplied maxima and the loop variables in Algorithms 3 and 4 is confusing; use Nmax and Kmax for the input bounds.
  4. [Figure 6] Figure 6 does not state whether the time axis is logarithmic and does not label the attack time units; adding axis labels and a legend for the fabric configurations would help.
  5. [Table 3] Table 3's header ('Time [s]||R|| Time [s]||C|| Time [s] # OpenFPGA runs ||S||') is hard to parse because the column separators are ambiguous; reformat with explicit columns for each phase.
  6. [Artifact availability] No artifact availability statement or repository link is given; for a tool flow paper, releasing scripts and configuration files would substantially aid reproducibility.

Circularity Check

1 steps flagged · score 2.0 of 10

No definitional circularity; the central overhead claim is an external empirical comparison, with only mild in-sample heuristic design keeping the score low.

  1. other [Section 6.2, 'Heuristics Evaluation' (heuristic objective adopted from the same benchmark corpus later used for validation)]
    "As the number of best solutions that do not have minimum tile numbers is marginal, we search for the solutions with minimum tile numbers."

    The core search objective of the NK/KN heuristics (minimize the OpenFPGA tile count) was adopted because the paper's own exhaustive runs on the same seven benchmarks showed that minimum-tile fabrics are almost always best. Table 2 then validates those heuristics against that same exhaustive benchmark data, so the heuristic-versus-exhaustive comparison is in-sample rather than an independent prediction. This is a mild self-referentiality in the evaluation design, not a by-construction identity: the reported area, power, and timing overheads are measured after synthesis and are not the quantity the heuristics optimize, so the headline 3.3x result still has independent empirical content.

full rationale

The central claim (up to 3.3x lower overheads and 4x higher utilization than ALICE's fixed fabric) is an empirical comparison against an external baseline, not the output of a fitted parameter. The NK/KN heuristics greedily minimize OpenFPGA tile count; they are not fitted to the later area/power/timing values, and the paper openly reports failure cases (22/291 clusters where a non-minimum-tile fabric has the minimum area, and GCD average relative costs above 4x). The security-utilization rationale behind Eq. (1) cites the authors' prior works [9,22], but the paper also runs its own IcySAT fabric-size evaluation, so the security premise does not reduce to a pure self-citation chain. The only notable issue is that the preliminary exhaustive analysis used to motivate the tile-count search space is the same benchmark corpus later used to validate the heuristics, making Section 6.2 partly in-sample. That is a methodological weakness rather than a definitional circularity, and it supports only a low score.

Assumptions & free parameters 1 free parameters · 3 assumptions · 0 invented entities

The central claims rest on CAD-tool fidelity, a SAT-timeout security proxy, and a tile-count heuristic proxy; no new physical entities or fitted constants are introduced.

free parameters (1)
  • eFPGA selection score weights in Equation 1 = 1.0 for normalized I/O utilization term and 1.0 for normalized CLB utilization term
    Chosen by hand to balance I/O and CLB utilization; no sensitivity analysis or independent justification is given, and this score determines which fabrics are selected in Algorithm 5.
assumptions (3)
  • domain assumption OpenFPGA-generated eFPGA netlists synthesized with NanGate 45nm accurately represent real soft-eFPGA overheads.
    Section 5.4 and Section 6 use OpenFPGA area reports and Cadence synthesis results as the ground truth for comparing fabrics; no silicon validation is provided.
  • domain assumption A 48-hour IcySAT timeout on a given fabric size is a valid indicator that the fabric is secure against SAT-based attacks.
    Section 6.1 uses timeout as the security criterion for the pre-step; this is a standard but heuristic practice, not a security proof.
  • domain assumption The designer protects the scan chain (for example with fuses or DisORC), which the threat model requires to render all surveyed attacks unfeasible.
    Section 4 states this assumption; without it, the security benefit of the fabric disappears.

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Cite this review

Pith. "Pith review of ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction." pith.science (2026). https://pith.science/paper/6TB66XWI

@misc{pith2026250600857,
  author       = {Pith},
  title        = {Pith review of: ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/6TB66XWI}},
  note         = {Machine review of arXiv:2506.00857}
}
read the original abstract

In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft countermeasures is hard to achieve. Using embedded configurable logic allows designers to completely hide the functionality of selected design portions from parties that do not have access to the configuration string (bitstream). However, the design space of redacted solutions is huge, with trade-offs between the portions selected for redaction and the configuration of the configurable embedded logic. We propose ARIANNA, a complete flow that aids the designer in all the stages, from selecting the logic to be hidden to tailoring the bespoke fabrics for the configurable logic used to hide it. We present a security evaluation of the considered fabrics and introduce two heuristics for the novel bespoke fabric flow. We evaluate the heuristics against an exhaustive approach. We also evaluate the complete flow using a selection of benchmarks. Results show that using ARIANNA to customize the redaction fabrics yields up to 3.3x lower overheads and 4x higher eFPGA fabric utilization than a one-fits-all fabric as proposed in prior works.

Figures

Figures reproduced from arXiv: 2506.00857 by the authors.

Figure 1
Figure 1. FPGA redaction flow. Critical modules are replaced with custom eFPGA implementations. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. A general FPGA architecture and its constituent parts. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. ARIANNA leverages a state-of-the-art eFPGA design flow based on OpenFPGA [ [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: ARIANNA flow for automatic eFPGA-based redaction. [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: Example of a valid and invalid cluster on a module hierarchy tree. Each node represents a module. An arrow from A to B [PITH_FULL_IMAGE:figures/full_fig_p010_5.png]
Figure 6
Figure 6. Figure 6: SAT attack results [s]. Timeout is 48 hours. [PITH_FULL_IMAGE:figures/full_fig_p016_6.png]
Figure 7
Figure 7. Figure 7: Number of best results, average and standard deviation of distance from the best result for GCD (top row), Nautilus (middle [PITH_FULL_IMAGE:figures/full_fig_p017_7.png]
Figure 8
Figure 8. Figure 8: Area, Power, and Timing results. The proposed heuristics outperform the state of the art, reducing overheads. [PITH_FULL_IMAGE:figures/full_fig_p019_8.png]
Figure 9
Figure 9. Figure 9: Physical layouts of DES3 solutions using the NK heuristic. In both configurations, the redacted modules are the same, on the [PITH_FULL_IMAGE:figures/full_fig_p019_9.png]

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.