Dynamically scaling both FPGA core and block-RAM voltage rails in tandem, guided by resource-level libraries and workload prediction, yields about 4X power reduction over nominal operation and 33.6% improvement over single-rail DVFS.
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Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms
Dynamically scaling both FPGA core and block-RAM voltage rails in tandem, guided by resource-level libraries and workload prediction, yields about 4X power reduction over nominal operation and 33.6% improvement over single-rail DVFS.