EdgeSpike delivers 91.4% mean accuracy on five sensing tasks with 31x lower energy on neuromorphic hardware and 6.3x longer battery life in a seven-month field deployment compared to conventional CNNs.
SpiNNaker 2: A 10 million core processor system for brain simulation and machine learning
4 Pith papers cite this work. Polarity classification is still indexing.
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SNN workloads deployed via K3d show up to 47.6 times higher latency and 49 times lower throughput when CPU is limited to 0.5 cores, with accuracy staying stable but tail latency issues from round-robin routing during scaling.
A heterogeneous FPGA SoC integrates the open-source ReckOn recurrent SNN accelerator with X-HEEP RISC-V and Zynq ARM processors, validated for equivalent accuracy on classification tasks and online learning on Braille digits.
Neuromorphic computing using compute-in-memory, analog dynamics, and sparse brain-inspired communication offers a route to more energy-efficient AI beyond traditional CMOS scaling limits.
citing papers explorer
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EdgeSpike: Spiking Neural Networks for Low-Power Autonomous Sensing in Edge IoT Architectures
EdgeSpike delivers 91.4% mean accuracy on five sensing tasks with 31x lower energy on neuromorphic hardware and 6.3x longer battery life in a seven-month field deployment compared to conventional CNNs.
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Evaluating Container Orchestration for Neuromorphic Workloads in Virtual Edge Environments
SNN workloads deployed via K3d show up to 47.6 times higher latency and 49 times lower throughput when CPU is limited to 0.5 cores, with accuracy staying stable but tail latency issues from round-robin routing during scaling.
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Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
A heterogeneous FPGA SoC integrates the open-source ReckOn recurrent SNN accelerator with X-HEEP RISC-V and Zynq ARM processors, validated for equivalent accuracy on classification tasks and online learning on Braille digits.
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Neuromorphic Computing for Low-Power Artificial Intelligence
Neuromorphic computing using compute-in-memory, analog dynamics, and sparse brain-inspired communication offers a route to more energy-efficient AI beyond traditional CMOS scaling limits.