EdgeSpike delivers 91.4% mean accuracy on five sensing tasks with 31x lower energy on neuromorphic hardware and 6.3x longer battery life in a seven-month field deployment compared to conventional CNNs.
SpiNNaker 2: A 10 million core processor system for brain simulation and machine learning
5 Pith papers cite this work, alongside 89 external citations. Polarity classification is still indexing.
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Pith papers citing it
89
external citations · Pith
abstract
SpiNNaker is an ARM-based processor platform optimized for the simulation of spiking neural networks. This brief describes the roadmap in going from the current SPINNaker1 system, a 1 Million core machine in 130nm CMOS, to SpiNNaker2, a 10 Million core machine in 22nm FDSOI. Apart from pure scaling, we will take advantage of specific technology features, such as runtime adaptive body biasing, to deliver cutting-edge power consumption. Power management of the cores allows a wide range of workload adaptivity, i.e. processor power scales with the complexity and activity of the spiking network. Additional numerical accelerators will enhance the utility of SpiNNaker2 for simulation of spiking neural networks as well as for executing conventional deep neural networks. These measures should increase the simulation capacity of the machine by a factor $>$50. The interplay between the two domains, i.e. spiking and rate based, will provide an interesting field for algorithm exploration on SpiNNaker2. Apart from the platforms' traditional usage as a neuroscience exploration tool, the extended functionality opens up new application areas such as automotive AI, tactile internet, industry 4.0 and biomedical processing.
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A spiking ring-network model with dynamically controllable manifold geometry is deployed on SpiNNaker 2 hardware to drive closed-loop robotic maze navigation.
SNN workloads deployed via K3d show up to 47.6 times higher latency and 49 times lower throughput when CPU is limited to 0.5 cores, with accuracy staying stable but tail latency issues from round-robin routing during scaling.
A heterogeneous FPGA SoC integrates the open-source ReckOn recurrent SNN accelerator with X-HEEP RISC-V and Zynq ARM processors, validated for equivalent accuracy on classification tasks and online learning on Braille digits.
Neuromorphic computing using compute-in-memory, analog dynamics, and sparse brain-inspired communication offers a route to more energy-efficient AI beyond traditional CMOS scaling limits.
citing papers explorer
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EdgeSpike: Spiking Neural Networks for Low-Power Autonomous Sensing in Edge IoT Architectures
EdgeSpike delivers 91.4% mean accuracy on five sensing tasks with 31x lower energy on neuromorphic hardware and 6.3x longer battery life in a seven-month field deployment compared to conventional CNNs.
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Dynamic neural manifolds for flexible closed-loop control on neuromorphic hardware
A spiking ring-network model with dynamically controllable manifold geometry is deployed on SpiNNaker 2 hardware to drive closed-loop robotic maze navigation.
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Evaluating Container Orchestration for Neuromorphic Workloads in Virtual Edge Environments
SNN workloads deployed via K3d show up to 47.6 times higher latency and 49 times lower throughput when CPU is limited to 0.5 cores, with accuracy staying stable but tail latency issues from round-robin routing during scaling.
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Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
A heterogeneous FPGA SoC integrates the open-source ReckOn recurrent SNN accelerator with X-HEEP RISC-V and Zynq ARM processors, validated for equivalent accuracy on classification tasks and online learning on Braille digits.
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Neuromorphic Computing for Low-Power Artificial Intelligence
Neuromorphic computing using compute-in-memory, analog dynamics, and sparse brain-inspired communication offers a route to more energy-efficient AI beyond traditional CMOS scaling limits.