pith. sign in

arxiv: 2604.04727 · v1 · submitted 2026-04-06 · 💻 cs.AR · cs.AI

Neuromorphic Computing for Low-Power Artificial Intelligence

Keshava Katti , Pratik Chaudhari , Deep Jariwala This is my paper

Pith reviewed 2026-05-10 19:05 UTC · model grok-4.3

classification 💻 cs.AR cs.AI
keywords neuromorphic computingenergy efficiencycompute-in-memoryCMOS limitsanalog dynamicsbrain-inspired hardwarecross-layer co-designlow-power AI
0
0 comments X

The pith

Neuromorphic computing uses brain-inspired analog dynamics, sparse signaling, and compute-in-memory to push past the energy-efficiency limits of classical CMOS for AI workloads.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper states that classical CMOS scaling has run into hard physical barriers on energy use that cannot be fixed by making transistors smaller or denser. It claims neuromorphic hardware can break through those barriers by storing and processing data together in new non-volatile devices, using continuous analog signals instead of binary switching, and communicating only when needed in a brain-like sparse pattern. Achieving this gain is not a simple hardware swap; it demands simultaneous redesign of materials, device physics, mixed-signal circuits, and algorithms that match those physics. The stakes are high because AI training and inference already dominate data-center power budgets and will grow worse without new approaches. If the co-design works, AI systems could run the same tasks at far lower energy cost while remaining scalable to larger models.

Core claim

Classical computing is beginning to encounter fundamental limits of energy efficiency that can no longer be solved by increasing circuit density or refining standard semiconductor processes. By leveraging novel device modalities and compute-in-memory, in addition to analog dynamics and sparse communication inspired by the brain, neuromorphic computing offers a promising path toward improvements in the energy efficiency and scalability of current AI systems through a cross-layer co-design effort spanning new materials and non-volatile device structures, novel mixed-signal circuits and architectures, and learning algorithms tailored to the physics of these substrates.

What carries the argument

Cross-layer co-design that couples new non-volatile materials and devices with mixed-signal circuits and physics-matched learning algorithms to replace separate memory and processor blocks.

Load-bearing premise

That integrated redesign across materials, devices, circuits, and algorithms will actually overcome the fundamental energy limits of classical CMOS technology.

What would settle it

A side-by-side measurement on equivalent AI tasks showing that a complete neuromorphic prototype built from the surveyed materials and circuits uses at least as much energy per operation as the best-optimized digital CMOS system.

Figures

Figures reproduced from arXiv: 2604.04727 by Deep Jariwala, Keshava Katti, Pratik Chaudhari.

Figure 1
Figure 1. Figure 1: Comparison of classical and neuromorphic computer architectures. Source: (Kim, Karpov, et al. 2023). Current Challenges to Classical Computing Current scaling trends of AI hardware are becoming prohibitive with respect to power consumption and cost. Specifically, communication cost is associated with existing von Neumann architecture, which represents any stored-program computer for which the fetch instruc… view at source ↗
read the original abstract

Classical computing is beginning to encounter fundamental limits of energy efficiency. This presents a challenge that can no longer be solved by strategies such as increasing circuit density or refining standard semiconductor processes. The growing computational and memory demands of artificial intelligence (AI) require disruptive innovation in how information is represented, stored, communicated, and processed. By leveraging novel device modalities and compute-in-memory (CIM), in addition to analog dynamics and sparse communication inspired by the brain, neuromorphic computing offers a promising path toward improvements in the energy efficiency and scalability of current AI systems. But realizing this potential is not a matter of replacing one chip with another; rather, it requires a co-design effort, spanning new materials and non-volatile device structures, novel mixed-signal circuits and architectures, and learning algorithms tailored to the physics of these substrates. This article surveys the key limitations of classical complementary metal-oxide-semiconductor (CMOS) technology and outlines how such cross-layer neuromorphic approaches may overcome them.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

0 major / 3 minor

Summary. This manuscript is a survey that reviews the energy-efficiency limits of classical CMOS technology under growing AI workloads and sketches neuromorphic alternatives based on novel device modalities, compute-in-memory (CIM), analog dynamics, and brain-inspired sparse communication. It concludes that realizing gains requires cross-layer co-design spanning materials, non-volatile devices, mixed-signal circuits, and tailored algorithms.

Significance. The paper synthesizes established neuromorphic concepts into a coherent high-level narrative and explicitly credits the necessity of co-design across layers, which is a standard but important observation in the field. Because the manuscript contains no new derivations, benchmarks, machine-checked proofs, or falsifiable predictions, its significance is limited to providing an accessible overview rather than advancing the state of the art.

minor comments (3)
  1. [Abstract] Abstract: the phrase 'fundamental limits of energy efficiency' is stated without a single numerical reference (e.g., pJ/op or TOPS/W figures from recent CMOS AI accelerators); adding one or two concrete citations would strengthen the motivation.
  2. The survey would benefit from a short table or paragraph contrasting reported energy efficiencies of representative CMOS versus neuromorphic prototypes drawn from the cited literature.
  3. A dedicated subsection on open challenges (device variability, programming overhead, system-level integration) would balance the optimistic tone and better serve readers.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their review and for recommending minor revision. The manuscript is a survey paper, and we address the referee's observations on its scope and significance below.

read point-by-point responses

  1. Referee: The paper synthesizes established neuromorphic concepts into a coherent high-level narrative and explicitly credits the necessity of co-design across layers, which is a standard but important observation in the field. Because the manuscript contains no new derivations, benchmarks, machine-checked proofs, or falsifiable predictions, its significance is limited to providing an accessible overview rather than advancing the state of the art.

    Authors: We agree that the manuscript is a survey synthesizing established concepts in neuromorphic computing and does not introduce new derivations, benchmarks, or proofs. Our goal was to provide a coherent high-level narrative connecting CMOS energy-efficiency limits with neuromorphic alternatives (CIM, analog dynamics, sparse communication) while stressing the need for cross-layer co-design. We view such integrative overviews as valuable for an interdisciplinary audience, even without new empirical contributions. We have made no changes to add new results, as this would change the paper's intended nature as a review. revision: no

Circularity Check

0 steps flagged

No significant circularity

full rationale

The paper is a descriptive survey reviewing CMOS energy limits and sketching neuromorphic co-design approaches drawn from prior literature. It contains no original derivations, equations, quantitative predictions, or falsifiable claims whose validity could reduce to fitted inputs or self-citations. The central statement is explicitly descriptive ('offers a promising path') rather than a derivation chain, so none of the enumerated circularity patterns apply.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

As a survey paper, the content rests on the accuracy and representativeness of the cited literature rather than any new parameters, axioms, or entities introduced by the authors.

pith-pipeline@v0.9.0 · 5461 in / 996 out tokens · 50535 ms · 2026-05-10T19:05:34.636344+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

What do these tags mean?
matches
The paper's claim is directly supported by a theorem in the formal canon.
supports
The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends
The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses
The paper appears to rely on the theorem as machinery.
contradicts
The paper's claim conflicts with a theorem or certificate in the canon.
unclear
Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

46 extracted references · 46 canonical work pages

  1. [1]

    IEEE Transactions on Comput

    TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Trans Comput-Aided Des Integr Circuits Syst. 34(10):1537–1557. doi:10.1109/TCAD.2015.2474396. Balasubramanian V

    work page doi:10.1109/tcad.2015.2474396 2015

  2. [2]

    Balasubramanian

    Brain power. Proc Natl Acad Sci. 118(32):e2107022118. doi:10.1073/pnas.2107022118. Boahen K

    work page doi:10.1073/pnas.2107022118

  3. [3]

    Comput Sci Eng

    A neuromorph’s prospectus. Comput Sci Eng. 19(2):14–28. doi:10.1109/MCSE.2017.33. 13 Boahen K

    work page doi:10.1109/mcse.2017.33 2017

  4. [4]

    Dendrocentric learning for synthetic intelligence. Nature. 612(7938):43–50. doi:10.1038/s41586-022-05340-6. Burr GW, Breitwisch MJ, Franceschini M, Garetto D, Gopalakrishnan K, Jackson B, Kurdi B, Lam C, Lastras LA, Padilla A, et al

    work page doi:10.1038/s41586-022-05340-6

  5. [5]

    J Vac Sci Technol B

    Phase change memory technology. J Vac Sci Technol B. 28(2):223–262. doi:10.1116/1.3301579. Custom ASIC | Process Design Kit (PDK) & IP Design | SkyWater

    work page doi:10.1116/1.3301579

  6. [6]

    [accessed 2025 Nov 19]

    Skywater Technol. [accessed 2025 Nov 19]. https://www.skywatertechnology.com/technology-and-design- enablement/. Decadal Plan for Semiconductors - SRC. [accessed 2025 Nov 12]. https://www.src.org/about/decadal-plan/. Fellous-Asiani M, Chai JH, Thonnart Y , Ng HK, Whitney RS, Auffèves A

    work page 2025

  7. [7]

    doi:10.1103/PRXQuantum.4.040319

    Optimizing resource efficiencies for scalable full-stack quantum computers. doi:10.1103/PRXQuantum.4.040319. [accessed 2025 Nov 17]. http://arxiv.org/abs/2209.05469. Fichtner S, Wolff N, Lofink F, Kienle L, Wagner B

    work page doi:10.1103/prxquantum.4.040319 2025

  8. [8]

    AlScN: A III –V semiconductor based ferroelectric,

    AlScN: A III-V semiconductor based ferroelectric. J Appl Phys. 125(11):114103. doi:10.1063/1.5084945. Ghosh S, Zheng Y , Zhang Z, Sun Y , Schranghamer TF, Sakib NU, Oberoi A, Chen C, Redwing JM, Yang Y , et al

    work page doi:10.1063/1.5084945

  9. [9]

    Nat Electron

    Monolithic and heterogeneous three-dimensional integration of two- dimensional materials with high-density vias. Nat Electron. 7(10):892–903. doi:10.1038/s41928- 024-01251-8. Han Z, Chen C-C, Pradhan DK, Moore DC, Gudavalli R, Yang X, Kim K-H, Cho H, Anderson Z, Ware S, et al

    work page doi:10.1038/s41928-

  10. [10]

    Kilobyte-scale, selector-free, thermally robust AlScN ferroelectric diode crossbar arrays. Device. 0(0). doi:10.1016/j.device.2025.100974. [accessed 2025 Nov 12]. https://www.cell.com/device/abstract/S2666-9986(25)00287-X. He Y , Moore DC, Wang Y , Ware S, Ma S, Pradhan DK, Hu Z, Du X, Kennedy WJ, Glavin NR, et al

    work page doi:10.1016/j.device.2025.100974 2025

  11. [11]

    Al₀.₆₈Sc₀.₃₂N/SiC -based metal -ferroelectric-semiconductor capacitors operating up to 1000 °C,

    Al0.68Sc0.32N/SiC-Based Metal-Ferroelectric-Semiconductor Capacitors Operating up to 1000 °C. Nano Lett. 25(12):4767–4773. doi:10.1021/acs.nanolett.4c06178. Ho A, Erdil E, Besiroglu T

    work page doi:10.1021/acs.nanolett.4c06178

  12. [12]

    doi:10.48550/arXiv.2312.08595

    Limits to the Energy Efficiency of CMOS Microprocessors. doi:10.48550/arXiv.2312.08595. [accessed 2025 Nov 17]. http://arxiv.org/abs/2312.08595. Hu Z, Cho H, Rai RK, Bao K, Zhang Y , Qu Z, He Y , Ji Y , Leblanc C, Kim K-H, et al

    work page doi:10.48550/arxiv.2312.08595 2025

  13. [13]

    Demonstration of Highly Scaled AlScN Ferroelectric Diode Memory with a Storage Density of > 100 Mbit/mm²,

    Demonstration of Highly Scaled AlScN Ferroelectric Diode Memory with a Storage Density of >100 Mbit/mm2. Nano Lett. 25(37):13748–13755. doi:10.1021/acs.nanolett.5c02961. Ielmini D, Wong H-SP

    work page doi:10.1021/acs.nanolett.5c02961

  14. [14]

    In-Memory Computing with Resistive Switching Devices

    In-memory computing with resistive switching devices. Nat Electron. 1(6):333–343. doi:10.1038/s41928-018-0092-2. Intel

    work page doi:10.1038/s41928-018-0092-2

  15. [15]

    E., Sameshima, K., Baccala, L

    Spiking Manifesto. doi:10.48550/arXiv.2512.11843. [accessed 2025 Dec 24]. http://arxiv.org/abs/2512.11843. Jayachandran D, Oberoi A, Sebastian A, Choudhury TH, Shankar B, Redwing JM, Das S

    work page doi:10.48550/arxiv.2512.11843 2025

  16. [16]

    Nat Electron

    A low-power biomimetic collision detector based on an in-memory molybdenum disulfide photodetector. Nat Electron. 3(10):646–655. doi:10.1038/s41928-020-00466-9. Kim K-H, Han Z, Zhang Y , Musavigharavi P, Zheng J, Pradhan DK, Stach EA, Olsson RHI, Jariwala D

    work page doi:10.1038/s41928-020-00466-9

  17. [17]

    ACS Nano

    Multistate, Ultrathin, Back-End-of-Line-Compatible AlScN Ferroelectric Diodes. ACS Nano. 18(24):15925–15934. doi:10.1021/acsnano.4c03541. Kim K-H, Karpov I, Olsson RH, Jariwala D

    work page doi:10.1021/acsnano.4c03541

  18. [18]

    Nat Nanotechnol

    Wurtzite and fluorite ferroelectric materials for electronic memory. Nat Nanotechnol. 18(5):422–441. doi:10.1038/s41565-023-01361-y. Kim K-H, Oh S, Fiagbenu MMA, Zheng J, Musavigharavi P, Kumar P, Trainor N, Aljarb A, Wan Y , Kim HM, et al

    work page doi:10.1038/s41565-023-01361-y

  19. [19]

    Nat Nanotechnol

    Scalable CMOS back-end-of-line-compatible AlScN/two-dimensional channel ferroelectric field-effect transistors. Nat Nanotechnol. 18(9):1044–1050. doi:10.1038/s41565-023-01399-y. Lanza M, Wong H-SP, Pop E, Ielmini D, Strukov D, Regan BC, Larcher L, Villena MA, Yang JJ, Goux L, et al

    work page doi:10.1038/s41565-023-01399-y

  20. [20]

    Adv Electron Mater

    Recommended Methods to Study Resistive Switching Devices. Adv Electron Mater. 5(1):1800143. doi:10.1002/aelm.201800143. Le Gallo M, Khaddam-Aljameh R, Stanisavljevic M, Vasilopoulos A, Kersting B, Dazzi M, Karunaratne G, Brändli M, Singh A, Müller SM, et al

    work page doi:10.1002/aelm.201800143

  21. [21]

    Nat Electron

    A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. Nat Electron. 6(9):680–693. doi:10.1038/s41928-023-01010-1. Levy WB, Calvert VG

    work page doi:10.1038/s41928-023-01010-1

  22. [22]

    Seth Lloyd

    Communication consumes 35 times more energy than computation in the human cortex, but both costs are needed to predict synapse number. Proc Natl Acad Sci. 118(18):e2008173118. doi:10.1073/pnas.2008173118. Liu M, Wong H-SP

    work page doi:10.1073/pnas.2008173118

  23. [23]

    [accessed 2025 Dec 23]

    Toward a Trillion Transistors - IEEE Spectrum. [accessed 2025 Dec 23]. https://spectrum.ieee.org/trillion-transistor-gpu. Liu X, Katti K, Jariwala D

    work page 2025

  24. [24]

    6(5):1348–1365

    Accelerate and actualize: Can 2D materials bridge the gap between neuromorphic hardware and the human brain? Matter. 6(5):1348–1365. doi:10.1016/j.matt.2023.03.016. Liu X, Ting J, He Y , Fiagbenu MMA, Zheng J, Wang D, Frost J, Musavigharavi P, Esteves G, Kisslinger K, et al

    work page doi:10.1016/j.matt.2023.03.016 2023

  25. [25]

    Nano Lett

    Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes. Nano Lett. 22(18):7690–7698. doi:10.1021/acs.nanolett.2c03169. Liu X, Zheng J, Wang D, Musavigharavi P, Stach EA, Olsson R III, Jariwala D

    work page doi:10.1021/acs.nanolett.2c03169

  26. [26]

    Appl Phys Lett

    Aluminum scandium nitride-based metal–ferroelectric–metal diode memory devices with high on/off ratios. Appl Phys Lett. 118(20):202901. doi:10.1063/5.0051940. 15 Marinella MJ, Agarwal S

    work page doi:10.1063/5.0051940

  27. [27]

    Nat Electron

    Efficient reservoir computing with memristors. Nat Electron. 2(10):437–438. doi:10.1038/s41928-019-0318-y. Mayr C, Hoeppner S, Furber S

    work page doi:10.1038/s41928-019-0318-y

  28. [28]

    SpiNNaker 2: A 10 million core processor system for brain simulation and machine learning

    SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning. doi:10.48550/arXiv.1911.02385. [accessed 2025 Oct 13]. http://arxiv.org/abs/1911.02385. Mead C

    work page doi:10.48550/arxiv.1911.02385 1911

  29. [29]

    Reading, Mass

    Analog VLSI and neural systems. Reading, Mass. : Addison-Wesley. [accessed 2025 Nov 13]. http://archive.org/details/analogvlsineural00mead. Muir DR, Sheik S

    work page 2025

  30. [30]

    Nat Commun

    The road to commercial success for neuromorphic technologies. Nat Commun. 16(1):3586. doi:10.1038/s41467-025-57352-1. NVIDIA

    work page doi:10.1038/s41467-025-57352-1

  31. [31]

    NVIDIA H100 GPU. NVIDIA. [accessed 2025 Dec 26]. https://www.nvidia.com/en-au/data-center/h100/. Paredes-Vallés F, Hagenaars JJ, Dupeyroux J, Stroobants S, Xu Y , de Croon GCHE

    work page 2025

  32. [32]

    Fully neuromorphic vision and control for autonomous drone flight,

    Fully neuromorphic vision and control for autonomous drone flight. Sci Robot. 9(90):eadi0591. doi:10.1126/scirobotics.adi0591. Pehle C, Billaudelle S, Cramer B, Kaiser J, Schreiber K, Stradmann Y , Weis J, Leibfried A, Müller E, Schemmel J

    work page doi:10.1126/scirobotics.adi0591

  33. [33]

    Neurosci.16, 795876, DOI: 10.3389/fnins.2022.795876 (2022)

    doi:10.3389/fnins.2022.795876. [accessed 2025 Oct 13]. https://www.frontiersin.org/journals/neuroscience/articles/10.3389/fnins.2022.795876/full. Pradhan DK, Moore DC, Kim G, He Y , Musavigharavi P, Kim K-H, Sharma N, Han Z, Du X, Puli VS, et al

    work page doi:10.3389/fnins.2022.795876 2022

  34. [34]

    Nat Electron

    A scalable ferroelectric non-volatile memory operating at 600 °C. Nat Electron. 7(5):348–355. doi:10.1038/s41928-024-01148-6. Ravichandran H, Knobloch T, Subbulakshmi Radhakrishnan S, Wilhelmer C, Stepanoff SP, Stampfer B, Ghosh S, Oberoi A, Waldhoer D, Chen C, et al

    work page doi:10.1038/s41928-024-01148-6

  35. [35]

    Life and death of colloidal bonds control the rate-dependent rheology of gels

    A stochastic encoder using point defects in two-dimensional materials. Nat Commun. 15(1):10562. doi:10.1038/s41467- 024-54283-1. Rehman MM, Rehman HMMU, Gul JZ, Kim WY , Karimov KS, Ahmed N

    work page doi:10.1038/s41467-

  36. [36]

    Sci Technol Adv Mater

    Decade of 2D- materials-based RRAM devices: a review. Sci Technol Adv Mater. 21(1):147–186. doi:10.1080/14686996.2020.1730236. Rupp K

    work page doi:10.1080/14686996.2020.1730236 2020

  37. [37]

    [accessed 2025 Nov 19]

    CPU, GPU and MIC Hardware Characteristics over Time | Karl Rupp. [accessed 2025 Nov 19]. https://www.karlrupp.net/2013/06/cpu-gpu-and-mic-hardware-characteristics- over-time/. Rupp K

    work page 2025

  38. [38]

    [accessed 2025 Nov 12]

    karlrupp/microprocessor-trend-data. [accessed 2025 Nov 12]. https://github.com/karlrupp/microprocessor-trend-data. Sarkar S, Liu X, Jariwala D

    work page 2025

  39. [39]

    12(2):291–300

    Can a ferroelectric diode be a selector-less, universal, non- volatile memory? MRS Energy Sustain. 12(2):291–300. doi:10.1557/s43581-025-00137-2. 16 Schranghamer TF, Pannone A, Kumar JM, Thiyyadi Baiju DK, Chen C, McKnight T, Tadekawa S, Haines E, Ordonez R, Hayashi C, et al

    work page doi:10.1557/s43581-025-00137-2

  40. [40]

    Nat Commun

    Large-scale crossbar arrays based on three- terminal MoS2 memtransistors. Nat Commun. 16(1):9518. doi:10.1038/s41467-025-64536-2. Song S, Pradhan DK, Hu Z, Zhang Y , Keneipp RN, Susner MA, Bhattacharya P, Drndić M, Olsson RH, Jariwala D

    work page doi:10.1038/s41467-025-64536-2

  41. [41]

    doi:10.48550/arXiv.2503.19491

    Observation of giant remnant polarization in ultrathin AlScN at cryogenic temperatures. doi:10.48550/arXiv.2503.19491. [accessed 2025 Nov 12]. http://arxiv.org/abs/2503.19491. Technology-alt. Celest AI. [accessed 2025 Nov 12]. https://www.celestial.ai/technology-1. Traversi G, Gaioni L, Ratti L, Re V , Riceputi E

    work page doi:10.48550/arxiv.2503.19491 2025

  42. [42]

    Trochatos T, Kang C, Chong FT, Szefer J

    doi:10.1109/TNS.2024.3382348. Trochatos T, Kang C, Chong FT, Szefer J

    work page doi:10.1109/tns.2024.3382348 2024

  43. [43]

    In: 2025 26th International Symposium on Quality Electronic Design (ISQED)

    Exploration of Vulnerabilities of Fault-Tolerant Quantum Computing. In: 2025 26th International Symposium on Quality Electronic Design (ISQED). p. 1–6. [accessed 2025 Nov 17]. https://ieeexplore.ieee.org/document/11014388. Yu S, Jiang H, Huang S, Peng X, Lu A

    work page arXiv 2025

  44. [44]

    IEEE Circuits Syst Mag

    Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects. IEEE Circuits Syst Mag. 21(3):31–56. doi:10.1109/MCAS.2021.3092533. Zahoor F, Azni Zulkifli TZ, Khanday FA

    work page doi:10.1109/mcas.2021.3092533 2021

  45. [45]

    Nanoscale Res Lett

    Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications. Nanoscale Res Lett. 15(1):90. doi:10.1186/s11671-020-03299-9. Zhu L, Mangan M, Webb B

    work page doi:10.1186/s11671-020-03299-9

  46. [46]

    Sci Robot

    Neuromorphic sequence learning with an event camera on routes through vegetation. Sci Robot. 8(82):eadg3679. doi:10.1126/scirobotics.adg3679

    work page doi:10.1126/scirobotics.adg3679