Proposes encoding continuous variables in single-qubit amplitudes with amplitude estimation readout for qubit-efficient variational continuous optimization on standard qubit hardware.
Canonical reference
AbuGhanem, IBM Quantum Computers: Evo- lution, Performance, and Future Directions, preprint arXiv:2410.00916 (2024)
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HBR decomposition quantifies per-phase fidelity loss in quantum compilers, revealing that routing causes up to 60% loss in search circuits while synthesis dominates Hamiltonian simulation, and correctly predicts SDK rankings on both simulation and real hardware.
PAEMS is a new adaptive qubit error model that reduces timelike, spacelike, and spacetime error correlations by 19.5×, 9.3×, and 5.2× on IBM QPUs while outperforming Google's SI1000 model by 58-73% across multiple platforms.
An exact positive-probability decomposition of thermal relaxation noise into Clifford gates and resets exists for T2 ≤ T1, with a negativity-free approximation that outperforms Pauli twirling for T2 > T1.
Modified Quantum Volume test uses restricted universal circuits to directly determine heavy outputs without exponential classical simulation cost.
New analytic and Monte Carlo-assisted method tightens energy-based boson truncation bounds, reducing volume dependence in (1+1)D scalar and (2+1)D U(1) gauge theories.
Provides a quantitative universal approximation theorem with error bounds for noisy quantum neural networks and tests on real hardware for quantitative finance.
Proposes a fabless-foundry ecosystem for superconducting quantum chips built on certified PDKs, SPICE-Q multiphysics modeling, parameterized cells, Q-EDA automation, and a quantum-IP market.
Compares QFT, GHZ, and W circuits on 4-10 qubits between simulator and IBM hardware to assess noise impact and hardware compatibility in the NISQ era.
citing papers explorer
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High Precision Qubit-Efficient Variational Continuous Optimization via Amplitude Estimation
Proposes encoding continuous variables in single-qubit amplitudes with amplitude estimation readout for qubit-efficient variational continuous optimization on standard qubit hardware.
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Per-Phase Fidelity Attribution for Quantum Compilers using HBR Decomposition
HBR decomposition quantifies per-phase fidelity loss in quantum compilers, revealing that routing causes up to 60% loss in search circuits while synthesis dominates Hamiltonian simulation, and correctly predicts SDK rankings on both simulation and real hardware.
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PAEMS: Precise and Adaptive Error Model for Superconducting Quantum Processors
PAEMS is a new adaptive qubit error model that reduces timelike, spacelike, and spacetime error correlations by 19.5×, 9.3×, and 5.2× on IBM QPUs while outperforming Google's SI1000 model by 58-73% across multiple platforms.
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Exact and Efficient Stabilizer Simulation of Thermal-Relaxation Noise for Quantum Error Correction
An exact positive-probability decomposition of thermal relaxation noise into Clifford gates and resets exists for T2 ≤ T1, with a negativity-free approximation that outperforms Pauli twirling for T2 > T1.
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Benchmarking quantum devices beyond classical capabilities
Modified Quantum Volume test uses restricted universal circuits to directly determine heavy outputs without exponential classical simulation cost.
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Tightening energy-based boson truncation bound using Monte Carlo-assisted methods
New analytic and Monte Carlo-assisted method tightens energy-based boson truncation bounds, reducing volume dependence in (1+1)D scalar and (2+1)D U(1) gauge theories.
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Quantitative Universal Approximation for Noisy Quantum Neural Networks
Provides a quantitative universal approximation theorem with error bounds for noisy quantum neural networks and tests on real hardware for quantitative finance.
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Fabless Quantum Chip Design and Commercial Production
Proposes a fabless-foundry ecosystem for superconducting quantum chips built on certified PDKs, SPICE-Q multiphysics modeling, parameterized cells, Q-EDA automation, and a quantum-IP market.
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Comparing a Few Qubit Systems for Superconducting Hardware Compatibility and Circuit Design Sensitivity in Qiskit
Compares QFT, GHZ, and W circuits on 4-10 qubits between simulator and IBM hardware to assess noise impact and hardware compatibility in the NISQ era.