A valley-aware co-simulation and noise-aware optimization of discrete cryogenic circuit settings achieves 99.99% average shuttling fidelity over 10 μm at 20 m/s with tens of μW power.
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Valley-Aware Optimal Control of Spin Shuttling Using Cryogenic Integrated Electronics
A valley-aware co-simulation and noise-aware optimization of discrete cryogenic circuit settings achieves 99.99% average shuttling fidelity over 10 μm at 20 m/s with tens of μW power.