A 0.5-V TSMC 0.18-um CMOS voltage-to-spike encoder achieves <5.6% linearity deviation over 0.1-0.4 V while consuming 22-180 nW and occupying 0.0074 mm².
A 4 -fJ/spike artificial neuron in 65 nm CMOS technology Front
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A 0.5-V Linear Neuromorphic Voltage-to-Spike Encoder Using a Bulk-Driven Transconductor
A 0.5-V TSMC 0.18-um CMOS voltage-to-spike encoder achieves <5.6% linearity deviation over 0.1-0.4 V while consuming 22-180 nW and occupying 0.0074 mm².