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arxiv: 2604.09315 · v1 · submitted 2026-04-10 · 💻 cs.AR · cs.NE

A 0.5-V Linear Neuromorphic Voltage-to-Spike Encoder Using a Bulk-Driven Transconductor

Meysam Akbari , Erika Covi , Kea-Tiong Tang This is my paper

Pith reviewed 2026-05-10 16:44 UTC · model grok-4.3

classification 💻 cs.AR cs.NE
keywords voltage-to-spike encoderbulk-driven transconductorneuromorphic circuitslow-power CMOSlinear voltage-to-frequencyDPI neuron0.5 V operation
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The pith

A tail-less bulk-driven transconductor with DPI neuron yields a linear voltage-to-spike encoder at 0.5 volts.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper presents a neuromorphic circuit that converts input voltages into spike rates with high linearity while running at an ultralow 0.5-volt supply. It achieves this by combining a bulk-driven transconductor that linearizes the voltage-to-current step with a DPI-based leaky-integrate-and-fire neuron that linearizes the current-to-spike step. Fabricated results in 0.18-micrometer CMOS show the output firing rate stays within 5.6 percent of ideal linearity across a 0.1-to-0.4-volt input window and draws between 22 and 180 nanowatts. A circuit with these traits could allow always-on analog front-ends in energy-scarce neuromorphic sensors without high-voltage rails or large batteries.

Core claim

The encoder achieves near-linear voltage-to-firing-rate conversion by pairing a linearized bulk-driven transconductor with a DPI-based LIF neuron. A tail-less bulk-driven differential pair improves large-signal linearity, while a translinear linearization network suppresses the dominant sinh nonlinearity and stabilizes the bias-tunable V-to-I gain. The resulting current feeds a DPI front-end that linearizes current-to-spike conversion. Fabricated in TSMC 0.18-um CMOS and operating at VDD = 0.5 V with 2-27 nA reference current, the encoder achieves a deviation of less than 5.6 percent from linearity over 0.1-0.4 V input, consumes 22-180 nW, and occupies 0.0074 mm².

What carries the argument

The linearized bulk-driven transconductor, which suppresses sinh nonlinearity via a translinear network to produce a stable, tunable current that the DPI neuron then converts linearly into spikes.

If this is right

  • The firing rate follows the input voltage with less than 5.6 percent deviation over the 0.1-0.4 V range.
  • Power draw stays between 22 nW and 180 nW depending on the chosen reference current.
  • The complete encoder fits in 0.0074 mm² of silicon at 0.5 V supply.
  • Reference current from 2 nA to 27 nA lets the voltage-to-spike gain be tuned after fabrication.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same linearization blocks could be reused in other low-voltage analog-to-digital or sensor interfaces.
  • Arrays of these encoders might form the front end of a larger neuromorphic processor for always-on edge sensing.
  • Pairing the encoder with on-chip digital spike processing could cut total system energy further than a conventional ADC approach.

Load-bearing premise

The measured linearity on the fabricated chip will continue to hold when the circuit experiences real process variation, temperature changes, and integration into a larger system.

What would settle it

A test that shows linearity deviation greater than 5.6 percent when the same encoder is measured across multiple temperature points or process corners on additional dies.

Figures

Figures reproduced from arXiv: 2604.09315 by Erika Covi, Kea-Tiong Tang, Meysam Akbari.

Figure 1
Figure 1. Figure 1: , is inspired by [7, 11]. The output current of the proposed transconductor is injected into the neuron through a differential pair integrator (DPI) at its input, composed of transistors M1-M3, rather than directly into the membrane node Vmem. Owing to the cascoded topology, the transconductor exhibits a high output impedance and therefore behaves approximately as a voltage-controlled current source over t… view at source ↗
Figure 2
Figure 2. Figure 2: shows the measurement setup. The differential input (Vi+–Vi-) is linearly converted to a single-ended current Iin by the transconductor and integrated onto the membrane capacitor Cm by the neuron. Output spikes are buffered to drive the PADs without loading. A differential amplifier in voltage-follower mode monitors the membrane potential, while an inverter chain buffers the spikes. The follower adds an es… view at source ↗
Figure 4
Figure 4. Figure 4: Measured DC transfer characteristics of the transconductor [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Measured frequency characteristics of the transconductor [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Measured output spikes for a triangular input voltage signal [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
read the original abstract

This work introduces an ultralow-power voltage-to-spike encoder that achieves near-linear voltage-to-firing-rate conversion by pairing a linearized bulk-driven transconductor with a DPI-based LIF neuron. A tail-less bulk-driven differential pair improves large-signal linearity, while a translinear linearization network suppresses the dominant sinh nonlinearity and stabilizes the bias-tunable V-to-I gain. The resulting current feeds a DPI front-end that linearizes current-to-spike conversion. Fabricated in TSMC 0.18-um CMOS and operating at VDD = 0.5 V with 2-27 nA reference current, the encoder achieves a deviation of less than 5.6 percent from linearity over 0.1-0.4 V input, consumes 22-180 nW, and occupies 0.0074 mm^2.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The manuscript presents a 0.5-V voltage-to-spike encoder for neuromorphic applications that combines a tail-less bulk-driven differential-pair transconductor with a translinear linearization network to suppress sinh nonlinearity and stabilize tunable V-to-I gain, followed by a DPI-based LIF neuron for linear current-to-spike conversion. Fabricated in TSMC 0.18 µm CMOS and measured at VDD = 0.5 V with reference currents of 2–27 nA, the design reports less than 5.6% deviation from linearity over a 0.1–0.4 V input range, power consumption of 22–180 nW, and an area of 0.0074 mm².

Significance. If the measured performance is reproducible, the work supplies a compact, sub-1 V, nanowatt-scale voltage-to-spike interface that could be useful for low-power neuromorphic sensor front-ends. The manuscript is strengthened by the inclusion of silicon measurement results from a fabricated chip rather than simulation-only validation; this provides direct empirical support for the linearity, power, and area claims.

major comments (1)
  1. [Measurement Results] Measurement Results section: The reported <5.6% linearity deviation, power range, and area are obtained from nominal fabricated-chip measurements, yet no multi-die statistics, standard deviations, Monte Carlo results, or corner/temperature data are presented. Because the central claim concerns a practical neuromorphic encoder whose linearization relies on the bulk-driven pair and translinear network, the absence of variation characterization leaves the robustness of the V-to-I gain stabilization unverified and limits the strength of the performance claims.
minor comments (2)
  1. [Abstract] Abstract and body: The abstract uses the qualitative term 'near-linear' while the results quantify <5.6% deviation; adopting consistent quantitative language throughout would improve precision.
  2. [Circuit Description] Circuit description: Bias-current values and transistor dimensions for the translinear network are referenced only by the 2–27 nA range; providing explicit sizing or a table would aid reproducibility.

Simulated Author's Rebuttal

1 responses · 1 unresolved

We thank the referee for the constructive feedback and positive assessment of the silicon-validated design. We address the concern on variation characterization below.

read point-by-point responses

  1. Referee: [Measurement Results] Measurement Results section: The reported <5.6% linearity deviation, power range, and area are obtained from nominal fabricated-chip measurements, yet no multi-die statistics, standard deviations, Monte Carlo results, or corner/temperature data are presented. Because the central claim concerns a practical neuromorphic encoder whose linearization relies on the bulk-driven pair and translinear network, the absence of variation characterization leaves the robustness of the V-to-I gain stabilization unverified and limits the strength of the performance claims.

    Authors: We agree that the presented results are from nominal measurements on a single fabricated die and that explicit variation analysis would strengthen the robustness claims for the bulk-driven transconductor and translinear network. In the revised manuscript we will add Monte Carlo simulation results (process and mismatch) for the V-to-I stage to quantify gain stability across corners. We note, however, that multi-die statistics, standard deviations from silicon, and temperature data are not available, as testing was limited to the available samples at room temperature. revision: partial

standing simulated objections not resolved
  • Measured multi-die statistics, standard deviations from silicon, and temperature-dependent data, which were not collected during the original fabrication and test campaign.

Circularity Check

0 steps flagged

No circularity; performance claims rest on fabricated-chip measurements, not derivations

full rationale

The manuscript presents a circuit design (bulk-driven transconductor + DPI LIF neuron) whose central performance claims—<5.6% linearity deviation over 0.1-0.4 V, 22-180 nW power, 0.0074 mm² area—are obtained directly from silicon measurements on TSMC 0.18 µm fabricated chips at VDD=0.5 V. No analytical derivation chain, fitted-parameter prediction, self-definitional equation, or load-bearing self-citation is invoked to obtain these numbers; the results are empirical and externally falsifiable by replication of the physical device. The design description contains standard circuit equations for transconductance and spike generation, but these serve only to motivate the topology and do not reduce to the reported metrics by construction.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The design rests on standard CMOS device physics and established circuit blocks; no new entities are postulated and the only adjustable quantities are the reference current range and supply voltage, which are operating parameters rather than fitted constants.

free parameters (1)
  • reference current (2-27 nA)
    Bias current range chosen to set the operating point and gain; not derived from first principles but selected for the target linearity and power.
axioms (1)
  • domain assumption Bulk-driven MOS transistors in 0.18-um CMOS obey the expected transconductance and nonlinearity models at 0.5 V supply
    Invoked to justify the linearization network performance.

pith-pipeline@v0.9.0 · 5453 in / 1313 out tokens · 27923 ms · 2026-05-10T16:44:18.842796+00:00 · methodology

discussion (0)

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Reference graph

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