An LLM-guided evolutionary workflow discovers 465 distinct bivariate bicycle and perturbed quantum LDPC codes at n ≤ 360, recovering known codes and reporting new examples such as [[288,16,12]].
Pereira and Vincent Steffan , year=
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Z_N bivariate-bicycle codes have essential topological properties determined by their Z_p prime-factor counterparts, enabling generalization of algebraic-geometric methods to anyon fusion rules and resolution of quasifractonic behavior via symmetry-enriched topological order.
BBS code dimension equals the algebraic multiplicity of finite nonzero common roots of the defining bivariate polynomials, enabling a root-based prescription for arbitrary boundary shapes that avoids corner corrections when edge conditions hold.
Barbell codes are a family of qLDPC codes with a matching superconducting chip layout enabling constant hardware complexity, simulated to preserve logical information over trillions of QEC cycles at 10^{-4} physical noise with under 30 data qubits per logical qubit.
citing papers explorer
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Evolutionary Discovery of Bivariate Bicycle Codes with LLM-Guided Search
An LLM-guided evolutionary workflow discovers 465 distinct bivariate bicycle and perturbed quantum LDPC codes at n ≤ 360, recovering known codes and reporting new examples such as [[288,16,12]].
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Symmetry-enriched topological order and quasifractonic behavior in $\mathbb{Z}_N$ stabilizer codes
Z_N bivariate-bicycle codes have essential topological properties determined by their Z_p prime-factor counterparts, enabling generalization of algebraic-geometric methods to anyon fusion rules and resolution of quasifractonic behavior via symmetry-enriched topological order.
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Algebra of Bivariate-Bicycle Surface Codes
BBS code dimension equals the algebraic multiplicity of finite nonzero common roots of the defining bivariate polynomials, enabling a root-based prescription for arbitrary boundary shapes that avoids corner corrections when edge conditions hold.
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Barbell Codes: qLDPC Codes for Superconducting Quantum Hardware
Barbell codes are a family of qLDPC codes with a matching superconducting chip layout enabling constant hardware complexity, simulated to preserve logical information over trillions of QEC cycles at 10^{-4} physical noise with under 30 data qubits per logical qubit.