A self-trained multi-agent RL framework pairs Verilog and Python agents for oracle-free mutual verification in RTL generation and reports 75.0% / 80.1% pass@1 on VerilogEval V2 using 4B / 9B models.
ChipBench: A next-step benchmark for evaluating LLM performance in AI-aided chip design
3 Pith papers cite this work. Polarity classification is still indexing.
3
Pith papers citing it
years
2026 3representative citing papers
ChipCraftBrain achieves 97.2% pass rate on VerilogEval and 94.7% on CVDP benchmarks for generating functional RTL code using adaptive multi-agent orchestration and hybrid reasoning.
CHIA is a distributed graph-based framework for composing, deploying, and verifying agentic AI hardware/software co-design flows, demonstrated on RTL, simulation, and compiler tasks.
citing papers explorer
-
ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
A self-trained multi-agent RL framework pairs Verilog and Python agents for oracle-free mutual verification in RTL generation and reports 75.0% / 80.1% pass@1 on VerilogEval V2 using 4B / 9B models.
-
ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
ChipCraftBrain achieves 97.2% pass rate on VerilogEval and 94.7% on CVDP benchmarks for generating functional RTL code using adaptive multi-agent orchestration and hybrid reasoning.
-
CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
CHIA is a distributed graph-based framework for composing, deploying, and verifying agentic AI hardware/software co-design flows, demonstrated on RTL, simulation, and compiler tasks.