MLLMs exhibit a Mirage effect by bypassing circuit diagrams in favor of header semantics for Verilog generation; VeriGround with identifier anonymization and D-ORPO training reaches 46% Functional Pass@1 while refusing blank images at >92%.
Large language model for verilog code generation: Literature review and the road ahead
4 Pith papers cite this work. Polarity classification is still indexing.
4
Pith papers citing it
years
2026 4verdicts
UNVERDICTED 4representative citing papers
RTLScout combines LLM-driven agentic RTL code optimization with synthesis and architecture sweeps to achieve 35% area and 45% delay reductions on a 16-bit IEEE-754 floating-point multiplier compared to baseline designs in ASAP7 technology.
COEVO unifies correctness and multi-objective PPA optimization in a single evolutionary loop for LLM RTL generation, reporting 97.5% and 94.5% Pass@1 on VerilogEval/RTLLM benchmarks plus best PPA on 43 of 49 designs.
VeriGraphi introduces a knowledge-graph-anchored multi-agent pipeline that produces reliable hierarchical synthesizable Verilog for complex designs such as RISC-V processors.
citing papers explorer
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From Mirage to Grounding: Towards Reliable Multimodal Circuit-to-Verilog Code Generation
MLLMs exhibit a Mirage effect by bypassing circuit diagrams in favor of header semantics for Verilog generation; VeriGround with identifier anonymization and D-ORPO training reaches 46% Functional Pass@1 while refusing blank images at >92%.
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RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits
RTLScout combines LLM-driven agentic RTL code optimization with synthesis and architecture sweeps to achieve 35% area and 45% delay reductions on a 16-bit IEEE-754 floating-point multiplier compared to baseline designs in ASAP7 technology.
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COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation
COEVO unifies correctness and multi-objective PPA optimization in a single evolutionary loop for LLM RTL generation, reporting 97.5% and 94.5% Pass@1 on VerilogEval/RTLLM benchmarks plus best PPA on 43 of 49 designs.
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VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
VeriGraphi introduces a knowledge-graph-anchored multi-agent pipeline that produces reliable hierarchical synthesizable Verilog for complex designs such as RISC-V processors.