An FPGA implementation of the DIF event filter achieves over 400 MEPS at 1280x720 with AUROC comparable to state-of-the-art denoising methods.
Barrios-Avil ´es, A
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.CV 1years
2025 1verdicts
CONDITIONAL 1representative citing papers
citing papers explorer
-
High Throughput Event Filtering: The Interpolation-based DIF Algorithm Hardware Architecture
An FPGA implementation of the DIF event filter achieves over 400 MEPS at 1280x720 with AUROC comparable to state-of-the-art denoising methods.