Empirical comparison of existing QDI asynchronous adder architectures in 32/28nm CMOS to highlight low-power and low-area options.
Varshavsky (Ed.), Self-Timed Control of Concurrent Processes: The Des ign of Aperiodic Logical Circuits in Computers and Discret e Systems , Chapter 4: Aperiodic Circuits, pp
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Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders
Empirical comparison of existing QDI asynchronous adder architectures in 32/28nm CMOS to highlight low-power and low-area options.