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arxiv: 1907.10826 · v1 · pith:L6ERX66Lnew · submitted 2019-07-24 · 💻 cs.AR

Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders

P Balasubramanian This is my paper

Pith reviewed 2026-05-24 16:41 UTC · model grok-4.3

classification 💻 cs.AR
keywords quasi-delay-insensitive addersasynchronous addersCMOS processlow power VLSIadder architecturesperformance comparison
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The pith

A comparison of quasi-delay-insensitive adders in 32/28nm CMOS points to architectures suitable for low power, energy, and area.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This technical note provides a performance comparison of quasi-delay-insensitive asynchronous adders from diverse architectures. The adders were all realized using a 32/28nm CMOS process. The objective is to highlight those suitable for low power and energy with less area in resource-constrained low power VLSI design scenarios. Non-QDI adders are not considered because they are not robust.

Core claim

QDI adders of various architectures were realized in 32/28nm CMOS and their design metrics compared to identify suitable options for low power/energy and reduced area.

What carries the argument

Quasi-delay-insensitive (QDI) adder architectures implemented in 32/28nm CMOS

Load-bearing premise

The QDI adders were implemented and simulated under equivalent conditions in the 32/28nm CMOS process.

What would settle it

A new set of simulations in the same 32/28nm process that changes which architectures appear best for power and area would falsify the results.

Figures

Figures reproduced from arXiv: 1907.10826 by P Balasubramanian.

Figure 1
Figure 1. Figure 1: (a) Transmitter-Receiver analogy of a QDI circuit stage, and (b) technical schematic portraying the example RTZ and RTO completion detectors for the presumed dual-rail data bus with inputs (X1, X0), (Y1, Y0) and (Z1, Z0). The OR gates and AND gates used in the RTZ and RTO completion detectors are the duals of each other. The datapath is highlighted by the red dashed line in (b). • First, the dual-rail data… view at source ↗
Figure 2
Figure 2. Figure 2: Input-output timing relation of different types of QDI circuits corresponding to (a) RTZ handshaking, and (b) RTO handshaking. The early set and reset behaviours of early output circuits are highlighted by the dotted green ovals in (a) and (b). A connection of strong-indication sub-circuits may not result in a strong-indication circuit; rather, a weak-indication circuit may result. For example, if two stro… view at source ↗
Figure 3
Figure 3. Figure 3: Longest signal propagation paths of QDI adders for application of data and spacer. FA refers to the Full Adder and SL refers to the Sum Logic (i.e., FA without the carry output) [PITH_FULL_IMAGE:figures/full_fig_p013_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Plots of normalized values of (a) CT and (b) PCTP of 32-bit QDI adders corresponding to RTZ handshaking. The adder legends are referenced from [PITH_FULL_IMAGE:figures/full_fig_p019_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Plots of normalized values of (a) CT and (b) PCTP of 32-bit QDI adders corresponding to RTO handshaking. The adder legends are referenced from [PITH_FULL_IMAGE:figures/full_fig_p020_5.png] view at source ↗
read the original abstract

In this technical note, we provide a comparison of the design metrics of various quasi-delay-insensitive (QDI) asynchronous adders, where the adders correspond to diverse architectures. QDI adders are robust, and the objective of this technical note is to point to those QDI adders which are suitable for low power/energy and less area. This information could be valuable for a resource-constrained low power VLSI design scenario. Non-QDI adders are excluded from the comparison since they are not robust although they may have optimized design metrics. All the QDI adders were realized using a 32/28nm CMOS process.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 0 minor

Summary. The paper is a technical note providing an empirical side-by-side comparison of design metrics (power, energy, area, delay) for multiple quasi-delay-insensitive (QDI) asynchronous adder architectures, all realized in the same 32/28nm CMOS process. Non-QDI adders are excluded. The goal is to identify which QDI adders are suitable for low-power/energy and reduced-area resource-constrained VLSI designs.

Significance. If the reported metrics reflect intrinsic architectural differences, the note supplies practical empirical guidance for selecting robust QDI adders in low-power scenarios. The work consists of an empirical side-by-side measurement of existing designs rather than new theory or proofs; its value is therefore conditional on the fairness of the implementation conditions.

major comments (1)
  1. [Abstract] Abstract: The central claim that the comparison identifies QDI adders 'suitable for low power/energy and less area' requires that the reported metrics reflect architectural differences. However, the statement that 'All the QDI adders were realized using a 32/28nm CMOS process' supplies no evidence (identical synthesis scripts, constraint files, place-and-route flows, or verification of equal design effort) that implementations were performed under strictly equivalent conditions. This is load-bearing for the ranking and recommendation.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback on our technical note. The single major comment is addressed point-by-point below. We will incorporate revisions to strengthen the description of implementation conditions.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central claim that the comparison identifies QDI adders 'suitable for low power/energy and less area' requires that the reported metrics reflect architectural differences. However, the statement that 'All the QDI adders were realized using a 32/28nm CMOS process' supplies no evidence (identical synthesis scripts, constraint files, place-and-route flows, or verification of equal design effort) that implementations were performed under strictly equivalent conditions. This is load-bearing for the ranking and recommendation.

    Authors: We agree that explicit documentation of equivalent implementation conditions is necessary to support the architectural comparison. All designs were realized in the identical 32/28 nm CMOS process using the same standard-cell library and commercial EDA tools; however, the manuscript does not currently detail the synthesis scripts, timing constraints, or place-and-route settings. We will revise the paper by adding a new subsection (likely in Section II or III) that describes the common design flow, including the synthesis constraints, optimization directives, and verification steps applied uniformly to every adder. The abstract will also be updated to reference this methodology section. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical comparison of existing designs

full rationale

The manuscript is a side-by-side empirical measurement of pre-existing QDI adder architectures realized in a common 32/28 nm process. No equations, fitted parameters, predictions derived from fits, self-citations used as load-bearing uniqueness theorems, or ansatzes are present in the provided text. The central claim rests on reported area/power/delay metrics rather than any derivation that reduces to its own inputs by construction. The noted concern about synthesis equivalence is a question of experimental control, not circularity in a claimed derivation chain.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The comparison rests on the domain assumption that QDI style guarantees robustness and on the choice of a single commercial process node; no free parameters or invented entities are introduced.

axioms (1)
  • domain assumption QDI adders are robust while non-QDI adders are not
    Explicitly invoked to justify exclusion of non-QDI designs.

pith-pipeline@v0.9.0 · 5621 in / 1053 out tokens · 29697 ms · 2026-05-24T16:41:37.938456+00:00 · methodology

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Reference graph

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