A parameter-extraction framework predicts ReRAM IMC performance across array sizes and resolutions to maximize energy efficiency under power and error limits without exhaustive simulations.
A 40-nm, 64-kb, 56.67 tops/w voltage-sensing computing-in-memory/digital rram macro supporting iterative write with verification and online read-disturb detection
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
eess.SY 1years
2026 1verdicts
UNVERDICTED 1representative citing papers
citing papers explorer
-
Design Space Exploration for ReRAM-based Architectures to Address Scaling Non-idealities
A parameter-extraction framework predicts ReRAM IMC performance across array sizes and resolutions to maximize energy efficiency under power and error limits without exhaustive simulations.