Pith. sign in

REVIEW

Security Analysis of Tunnel Field-Effect Transistor for Low Power Hardware

Not yet reviewed by Pith; the record is open.

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 1704.07878 v1 pith:YTF5CLEK submitted 2017-04-25 cs.CR

classification cs.CR
keywords securitytransistoradvantagesattackscomputingdesignenergyfield-effect
verification ladder T0 review T1 audit T2 compute T3 formal

Signed reviews

No signed human review yet.

0 comments
read the original abstract

Security and energy are considered as the most important parameters for designing and building a computing system nowadays. Today's attacks target different layers of the computing system (i.e. software and hardware). Introduction of new transistor technologies to the integrated circuits design is beneficial, especially for low energy requirements. The new devices have unique features and properties that provide security advantages. However, these properties may come to the aid of an adversary to design stronger attacks. Therefore, the advantages as well as the disadvantages of these technologies need to be well studied. This paper demonstrates the area and power efficiency of the tunnel field-effect transistor (TFET) technology along with analyzing its security aspects.

Discussion (0). Continue with ORCID to comment.

Pith tools