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arxiv: 1907.08863 · v1 · pith:6OZAOQ4Ynew · submitted 2019-07-20 · 💻 cs.CR

Defense-in-Depth: A Recipe for Logic Locking to Prevail

M Tanjidur Rahman , M Sazadur Rahman , Huanyu Wang , Shahin Tajik , Waleed Khalil , Farimah Farahmandi , Domenic Forte , Navid Asadizanjani
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Mark Tehranipoor
This is my paper

Pith reviewed 2026-05-24 18:37 UTC · model grok-4.3

classification 💻 cs.CR
keywords logic lockingdefense-in-depthhardware securityIP protectionoracle-guided attacksphysical attacks
0
0 comments X

The pith

Logic locking can achieve stronger protection by stacking independent countermeasures against oracle-guided, oracle-less, and physical attacks.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that single countermeasures leave logic locking vulnerable because each protects only against certain attack classes. It shows that a defense-in-depth structure, with multiple independent layers, can cover all three attack vectors at once by protecting the core components that hold or use the secret key. A sympathetic reader would care because the key is the sole barrier against IP theft in untrusted fabrication; once exposed, the locked design offers no security. The authors map the key components, classify the threats to each, propose layered defenses, and list open questions for combining the layers in practice.

Core claim

A multilayer defense model applied to logic locking delivers aggregated protection by placing independent countermeasures on the same device to block oracle-guided, oracle-less, and physical attacks simultaneously, where no prior single countermeasure had achieved this coverage.

What carries the argument

The defense-in-depth model, which stacks independent countermeasures to protect the locking key and its related circuit components from multiple threat classes.

If this is right

  • Core components such as key gates, key storage, and key distribution each require dedicated protection layers.
  • Vulnerabilities of those components can be grouped by whether the attacker has oracle access, lacks oracle access, or uses physical means.
  • Separate countermeasures can be assigned to each layer so that failure of one does not expose the key.
  • The approach leaves open questions on layer selection and integration that future work must resolve.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same multilayer pattern could be tested on other hardware-obfuscation methods that also rely on secret values.
  • Overhead measurements in area, power, and delay would be needed to check whether the combined layers remain practical for real chips.
  • If one layer introduces side-channel leakage that another layer cannot mask, the whole stack could still fail.

Load-bearing premise

Several independent countermeasures can be combined in one device to deliver aggregated protection against the three attack classes without creating new vulnerabilities or unacceptable overhead.

What would settle it

A demonstration that an attacker can extract the key by exploiting interactions or gaps between any two of the proposed defense layers when they are implemented together.

Figures

Figures reproduced from arXiv: 1907.08863 by Domenic Forte, Farimah Farahmandi, Huanyu Wang, Mark Tehranipoor, M Sazadur Rahman, M Tanjidur Rahman, Navid Asadizanjani, Shahin Tajik, Waleed Khalil.

Figure 1
Figure 1. Figure 1: Multiple protection layers in defense-in-depth [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: Simplified example of logic locking method. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Core components in an IC implemented with hardware [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Steps for developing a defense-in-depth model for logic locking. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: (a) Difference between before and after program of a TSMC eFuse structure in Qualcomm Gobi MDM9235 Modem [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: (a) FIB deposits Platinum in the milling cavity to [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) The input signal connected to the gate terminal of an n-MOSfet operating at T [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Attack methods for the core element in a logic locked chip. [PITH_FULL_IMAGE:figures/full_fig_p010_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Stake holders and corresponding IP threats in the horizontal supply chain. [PITH_FULL_IMAGE:figures/full_fig_p012_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: The threat model depending on asset and capability [PITH_FULL_IMAGE:figures/full_fig_p012_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Scattered reflection of incident laser beam in a [PITH_FULL_IMAGE:figures/full_fig_p015_12.png] view at source ↗
Figure 14
Figure 14. Figure 14: It detects the attack by measuring the additional capacitance introduced by the probe on selected sensitive wires. Compared to active shield which is covering a large chip area, the PAD approach is wire-oriented which is difficult to be applied to a large group of sensitive wires. Therefore, if only a few wires are identified as security-critical wires and need to be protected, PAD is a good option with s… view at source ↗
Figure 13
Figure 13. Figure 13: Working principle of active shield and bypass attack [PITH_FULL_IMAGE:figures/full_fig_p016_13.png] view at source ↗
Figure 15
Figure 15. Figure 15: Input encoder (left) and output decoder (right) for [PITH_FULL_IMAGE:figures/full_fig_p017_15.png] view at source ↗
read the original abstract

Logic locking has emerged as a promising solution for protecting the semiconductor intellectual Property (IP) from the untrusted entities in the design and fabrication process. Logic locking hides the functionality of the IP by embedding additional key-gates in the circuit. The correct output of the chip is produced, once the correct key value is available at the input of the key-gates. The confidentiality of the key is imperative for the security of the locked IP as it stands as the lone barrier against IP infringement. Therefore, the logic locking is considered as a broken scheme once the key value is exposed. The research community has shown the vulnerability of the logic locking techniques against different classes of attacks, such as Oracle-guided and physical attacks. Although several countermeasures have already been proposed against such attacks, none of them is simultaneously impeccable against Oracle-guided, Oracle-less, and physical attacks. Under such circumstances, a defense-in-depth approach can be considered as a practical approach in addressing the vulnerabilities of logic locking. Defense-in-depth is a multilayer defense approach where several independent countermeasures are implemented in the device to provide aggregated protection against different attack vectors. Introducing such a multilayer defense model in logic locking is the major contribution of this paper. With regard to this, we first identify the core components of logic locking schemes, which need to be protected. Afterwards, we categorize the vulnerabilities of core components according to potential threats for the locking key in logic locking schemes. Furthermore, we propose several defense layers and countermeasures to protect the device from those vulnerabilities. Finally, we turn our focus to open research questions and conclude with suggestions for future research directions.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 1 minor

Summary. The manuscript proposes a defense-in-depth strategy for logic locking to protect semiconductor IP. It identifies core components of locking schemes that must be secured, categorizes vulnerabilities according to oracle-guided, oracle-less, and physical attack vectors, suggests multiple independent defense layers and countermeasures to achieve aggregated protection, and concludes by listing open research questions and future directions.

Significance. If the proposed multilayer model could be shown to compose without new attack surfaces, key leakage, or prohibitive overhead, the shift from single-countermeasure logic locking to explicitly composable defenses would be a notable contribution to hardware security. The manuscript, however, supplies only categorization and high-level suggestions; no concrete architecture, interaction analysis, or overhead evaluation is provided, so the significance remains prospective rather than demonstrated.

major comments (3)
  1. [Abstract and defense-layers proposal section] Abstract (defense-in-depth paragraph) and the section proposing defense layers: the central claim that 'several independent countermeasures ... provide aggregated protection against different attack vectors' without 'new weaknesses' is load-bearing yet unsupported; the text supplies neither a composition analysis nor an example showing that the suggested layers avoid interference, fresh leakage paths, or unacceptable area/delay/power costs.
  2. [Core-components and vulnerability-categorization sections] Section identifying core components and categorizing vulnerabilities: while the categorization of threats to the locking key is useful, the manuscript does not map any proposed layer onto a specific core component with a concrete threat model that accounts for combined (oracle-guided + physical) attacks, leaving the independence assumption untested.
  3. [Open research questions section] Open-research-questions section: the practicality of the defense-in-depth recipe cannot be assessed because the manuscript contains no preliminary design sketch, even qualitative overhead discussion, or falsifiable prediction that would allow the community to evaluate whether the assumed non-interference actually obtains.
minor comments (1)
  1. [Abstract and introduction] The abstract and introduction would benefit from explicit citations to the specific prior countermeasures being layered, rather than generic references to 'several countermeasures have already been proposed.'

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the detailed and constructive review of our manuscript on a defense-in-depth strategy for logic locking. We address each major comment point by point below, clarifying the conceptual nature of the contribution while agreeing to strengthen certain aspects in revision.

read point-by-point responses

  1. Referee: [Abstract and defense-layers proposal section] Abstract (defense-in-depth paragraph) and the section proposing defense layers: the central claim that 'several independent countermeasures ... provide aggregated protection against different attack vectors' without 'new weaknesses' is load-bearing yet unsupported; the text supplies neither a composition analysis nor an example showing that the suggested layers avoid interference, fresh leakage paths, or unacceptable area/delay/power costs.

    Authors: The manuscript introduces defense-in-depth as a high-level paradigm for logic locking, analogous to its established use in other security domains where layers targeting distinct vectors are presumed to yield additive protection. The claim of aggregated protection without new weaknesses rests on the orthogonality of the categorized attack vectors (oracle-guided, oracle-less, physical) and the selection of countermeasures that address them separately. We agree that explicit discussion of composition, potential interference, and qualitative overhead would strengthen the presentation. In the revised manuscript we will expand the defense-layers section with such a discussion and a note on the need for future empirical validation. revision: yes

  2. Referee: [Core-components and vulnerability-categorization sections] Section identifying core components and categorizing vulnerabilities: while the categorization of threats to the locking key is useful, the manuscript does not map any proposed layer onto a specific core component with a concrete threat model that accounts for combined (oracle-guided + physical) attacks, leaving the independence assumption untested.

    Authors: The core-component identification and vulnerability categorization are meant to establish the assets requiring protection and the distinct threat classes. The proposed layers are positioned to map onto these components (e.g., key-storage protections against physical attacks, key-obfuscation techniques against oracle-guided attacks), with independence following from the differing attack surfaces. While a combined threat model is not developed in detail, the framework assumes that physical and functional protections can be applied without direct conflict. We will add an explicit mapping table in the revised version to illustrate layer-to-component assignments and briefly address combined-attack considerations. revision: yes

  3. Referee: [Open research questions section] Open-research-questions section: the practicality of the defense-in-depth recipe cannot be assessed because the manuscript contains no preliminary design sketch, even qualitative overhead discussion, or falsifiable prediction that would allow the community to evaluate whether the assumed non-interference actually obtains.

    Authors: The open-research-questions section is intentionally forward-looking; the paper's primary contribution is the identification of the defense-in-depth model and the open problems it raises rather than a concrete implementation. Adding a full design sketch or quantitative predictions would exceed the stated scope. Nevertheless, a qualitative illustration of layer application to a representative locking scheme would help readers assess the approach. We will therefore include such a high-level illustrative example in the revised manuscript. revision: partial

Circularity Check

0 steps flagged

No significant circularity; position paper relies on categorization without self-referential derivations

full rationale

The paper is a position paper whose contribution is the conceptual introduction of a defense-in-depth model for logic locking. It identifies core components, categorizes known attack classes from prior literature, and lists open questions. No equations, fitted parameters, predictions, or derivations appear that could reduce to inputs by construction. The multilayer claim is presented as a high-level recipe rather than a theorem or model whose independence is proven within the text. No self-citations function as load-bearing uniqueness theorems or ansatzes. The argument chain is therefore self-contained against external benchmarks of attack categories.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The proposal depends on domain assumptions about attack independence and the feasibility of non-interfering layers; no free parameters or new entities are introduced.

axioms (2)
  • domain assumption Logic locking security depends solely on key confidentiality as the lone barrier against IP infringement.
    Stated directly in the abstract.
  • ad hoc to paper Multiple independent countermeasures can be implemented to provide aggregated protection against different attack vectors without introducing new weaknesses.
    Central premise of the defense-in-depth model proposed in the abstract.

pith-pipeline@v0.9.0 · 5856 in / 1160 out tokens · 19170 ms · 2026-05-24T18:37:59.885094+00:00 · methodology

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Reference graph

Works this paper leans on

91 extracted references · 91 canonical work pages · 1 internal anchor

  1. [1]

    Epic: Ending piracy of integrated circuits,

    J. A. Roy, F. Koushanfar, and I. L. Markov, “Epic: Ending piracy of integrated circuits,” in Proceedings of the conference on Design, automation and test in Europe . ACM, 2008, pp. 1069–1074

    work page 2008

  2. [2]

    Harpoon: an obfuscation-based soc design methodology for hardware protection,

    R. S. Chakraborty and S. Bhunia, “Harpoon: an obfuscation-based soc design methodology for hardware protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 28, no. 10, pp. 1493–1502, 2009

    work page 2009

  3. [3]

    Security analysis of integrated circuit camouflaging,

    J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security analysis of integrated circuit camouflaging,” in Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security . ACM, 2013, pp. 709–720

    work page 2013

  4. [4]

    Evaluating the security of logic encryption algorithms,

    P. Subramanyan, S. Ray, and S. Malik, “Evaluating the security of logic encryption algorithms,” in 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) . IEEE, 2015, pp. 137–143

    work page 2015

  5. [5]

    Appsat: Approximately deobfuscating integrated circuits,

    K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y . Jin, “Appsat: Approximately deobfuscating integrated circuits,” in Hardware Oriented Security and Trust (HOST), 2017 IEEE International Symposium on . IEEE, 2017, pp. 95–100

    work page 2017

  6. [6]

    Removal attacks on logic locking and camouflaging techniques,

    M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran, “Removal attacks on logic locking and camouflaging techniques,” IEEE Transactions on Emerging Topics in Computing , 2017

    work page 2017

  7. [7]

    Security analysis of logic obfuscation,

    J. Rajendran, Y . Pino, O. Sinanoglu, and R. Karri, “Security analysis of logic obfuscation,” in Proceedings of the 49th Annual Design Automation Conference. ACM, 2012, pp. 83–89

    work page 2012

  8. [8]

    Anti-sat: Mitigating sat attack on logic locking,

    Y . Xie and A. Srivastava, “Anti-sat: Mitigating sat attack on logic locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2018

    work page 2018

  9. [9]

    Sarlock: Sat attack resistant logic locking,

    M. Yasin, B. Mazumdar, J. J. Rajendran, and O. Sinanoglu, “Sarlock: Sat attack resistant logic locking,” in 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) . IEEE, 2016, pp. 236–241

    work page 2016

  10. [10]

    Probing attacks on integrated circuits: Challenges and research opportunities,

    H. Wang, D. Forte, M. M. Tehranipoor, and Q. Shi, “Probing attacks on integrated circuits: Challenges and research opportunities,” IEEE Design Test, vol. 34, no. 5, pp. 63–71, Oct 2017

    work page 2017

  11. [11]

    Breaking and entering through the silicon,

    C. Helfmeier, D. Nedospasov, C. Tarnovsky, J. S. Krissler, C. Boit, and J.-P. Seifert, “Breaking and entering through the silicon,” in Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security. ACM, 2013, pp. 733–744

    work page 2013

  12. [12]

    On the power of optical contactless probing: Attacking bitstream encryption of fpgas,

    S. Tajik, H. Lohrke, J.-P. Seifert, and C. Boit, “On the power of optical contactless probing: Attacking bitstream encryption of fpgas,” in Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security. ACM, 2017, pp. 1661–1674

    work page 2017

  13. [13]

    The key is left under the mat: On the inappropriate security assumption of logic locking schemes,

    M. T. Rahman, S. Tajik, M. S. Rahman, M. Tehranipoor, and N. Asadizanjani, “The key is left under the mat: On the inappropriate security assumption of logic locking schemes,” Cryptology ePrint Archive, Report 2019/719, 2019, https://eprint.iacr.org/2019/719

    work page 2019

  14. [14]

    Circuit camouflage integration for hardware ip protection,

    R. P. Cocchi, J. P. Baukus, L. W. Chow, and B. J. Wang, “Circuit camouflage integration for hardware ip protection,” in Proceedings of the 51st Annual Design Automation Conference . ACM, 2014, pp. 1–5

    work page 2014

  15. [15]

    Comparative analysis of hardware obfuscation for ip protection,

    S. Amir, B. Shakya, D. Forte, M. Tehranipoor, and S. Bhunia, “Comparative analysis of hardware obfuscation for ip protection,” in Proceedings of the on Great Lakes Symposium on VLSI 2017 . ACM, 2017, pp. 363–368

    work page 2017

  16. [16]

    Ieee recommended practice for encryption and management of electronic design intellectual property,

    I. C. Society, “Ieee recommended practice for encryption and management of electronic design intellectual property,” https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7274481, accessed: 2017-09-30

    work page 2017

  17. [17]

    Stealthy dopant-level hardware trojans: extended version,

    G. T. Becker, F. Regazzoni, C. Paar, and W. P. Burleson, “Stealthy dopant-level hardware trojans: extended version,” Journal of Cryptographic Engineering, vol. 4, no. 1, pp. 19–31, 2014

    work page 2014

  18. [18]

    Cyclic obfuscation for creating sat-unresolvable circuits,

    K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y . Jin, “Cyclic obfuscation for creating sat-unresolvable circuits,” in Proceedings of the on Great Lakes Symposium on VLSI 2017 . ACM, 2017, pp. 173–178

    work page 2017

  19. [19]

    Covert gates: Protecting integrated circuits with undetectable camouflaging,

    B. Shakya, H. Shen, M. Tehranipoor, and D. Forte, “Covert gates: Protecting integrated circuits with undetectable camouflaging,” IACR Transactions on Cryptographic Hardware and Embedded Systems , pp. 86–118, 2019

    work page 2019

  20. [20]

    Camoperturb: secure ic camouflaging for minterm protection,

    M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran, “Camoperturb: secure ic camouflaging for minterm protection,” in 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) . IEEE, 2016, pp. 1–8

    work page 2016

  21. [21]

    Vanishing via for hardware ip protection from reverse engineering,

    S. Bhunia, H. Shen, M. M. Tehranipoor, D. J. Forte, and N. Asadizanjani, “Vanishing via for hardware ip protection from reverse engineering,” Jul. 12 2018, uS Patent App. 15/863,133

    work page 2018

  22. [22]

    Fault analysis-based logic encryption,

    J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y . Pino, O. Sinanoglu, and R. Karri, “Fault analysis-based logic encryption,” IEEE Transactions on computers, vol. 64, no. 2, pp. 410–424, 2015

    work page 2015

  23. [23]

    Preventing ic piracy using reconfigurable logic barriers,

    A. Baumgarten, A. Tyagi, and J. Zambreno, “Preventing ic piracy using reconfigurable logic barriers,” IEEE Design & Test of Computers , vol. 27, no. 1, 2010

    work page 2010

  24. [24]

    Physical design obfuscation of hardware: A comprehensive investigation of device and logic-level techniques,

    A. Vijayakumar, V . C. Patil, D. E. Holcomb, C. Paar, and S. Kundu, “Physical design obfuscation of hardware: A comprehensive investigation of device and logic-level techniques,” IEEE Transactions on Information Forensics and Security , vol. 12, no. 1, pp. 64–77, 2017

    work page 2017

  25. [25]

    The benefits of antifuse otp

    N. Chen, “The benefits of antifuse otp.” [Online]. Available: https://semiengineering.com/the-benefits-of-antifuse-otp/

    work page

  26. [26]

    Antifuse-based split-channel 1t-fuse bit cell for otp nvm ip

    Synopsys, “Antifuse-based split-channel 1t-fuse bit cell for otp nvm ip.” [Online]. Available: https://www.synopsys.com/dw/ipdir.php?ds=nvm 1t-bit-cell

    work page

  27. [27]

    Nand market hits speed bump

    M. LAPEDUS, “Nand market hits speed bump.” [Online]. Available: https://semiengineering.com/nand-market-hits-speed-bump/

    work page

  28. [28]

    Oxide charge measurements in eeprom devices,

    C. De Nardi, R. Desplats, P. Perdu, F. Beaudoin, and J.-L. Gauffier, “Oxide charge measurements in eeprom devices,” Microelectronics Reliability, vol. 45, no. 9-11, pp. 1514–1519, 2005

    work page 2005

  29. [29]

    Reverse engineering flash eeprom memories using scanning electron microscopy,

    F. Courbon, S. Skorobogatov, and C. Woods, “Reverse engineering flash eeprom memories using scanning electron microscopy,” in International Conference on Smart Card Research and Advanced Applications . Springer, 2016, pp. 57–72

    work page 2016

  30. [30]

    Laser fault attack on physically unclonable functions,

    S. Tajik, H. Lohrke, F. Ganji, J.-P. Seifert, and C. Boit, “Laser fault attack on physically unclonable functions,” in 2015 workshop on fault diagnosis and tolerance in cryptography (FDTC) . IEEE, 2015, pp. 85–96

    work page 2015

  31. [31]

    Key extraction using thermal laser stimulation,

    H. Lohrke, S. Tajik, T. Krachenfels, C. Boit, and J.-P. Seifert, “Key extraction using thermal laser stimulation,” IACR Transactions on Cryptographic Hardware and Embedded Systems , pp. 573–595, 2018

    work page 2018

  32. [32]

    Hardware security implications of reliability, remanence, and recovery in embedded memory,

    S. Skorobogatov, “Hardware security implications of reliability, remanence, and recovery in embedded memory,” Journal of Hardware and Systems Security , vol. 2, no. 4, pp. 314–321, 2018

    work page 2018

  33. [33]

    Probing assessment framework and evaluation of antiprobing solutions,

    H. Wang, Q. Shi, D. Forte, and M. M. Tehranipoor, “Probing assessment framework and evaluation of antiprobing solutions,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , pp. 1–14, 2019

    work page 2019

  34. [34]

    A call to action: Securing ieee 1687 and the need for an ieee test security standard,

    J. Dworak and A. Crouch, “A call to action: Securing ieee 1687 and the need for an ieee test security standard,” in 2015 IEEE 33rd VLSI Test Symposium (VTS). IEEE, 2015, pp. 1–4

    work page 2015

  35. [35]

    Cryptoscan: A secured scan chain architecture,

    D. Mukhopadhyay, S. Banerjee, D. RoyChowdhury, and B. B. Bhattacharya, “Cryptoscan: A secured scan chain architecture,” in 14th Asian Test Symposium (ATS’05) . IEEE, 2005, pp. 348–353

    work page 2005

  36. [36]

    Secure scan: A design-for-test architecture for crypto chips,

    B. Yang, K. Wu, and R. Karri, “Secure scan: A design-for-test architecture for crypto chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 25, no. 10, pp. 2287–2293, 2006

    work page 2006

  37. [37]

    A novel differential scan attack on advanced dft structures,

    J. D. Rolt, G. D. Natale, M.-L. Flottes, and B. Rouzeyre, “A novel differential scan attack on advanced dft structures,” ACM Transactions on Design Automation of Electronic Systems (TODAES) , vol. 18, no. 4, p. 58, 2013

    work page 2013

  38. [38]

    Design principles for tamper-resistant smartcard processors

    O. K ¨ommerling and M. G. Kuhn, “Design principles for tamper-resistant smartcard processors.” Smartcard, vol. 99, pp. 9–20, 1999. 20

    work page 1999

  39. [39]

    Secure scan techniques: a comparison,

    D. Hely, F. Bancel, M.-L. Flottes, and B. Rouzeyre, “Secure scan techniques: a comparison,” in 12th IEEE International On-Line Testing Symposium (IOLTS’06). IEEE, 2006, pp. 6–pp

    work page 2006

  40. [40]

    Ieee 1500 compatible secure test wrapper for embedded ip cores,

    G.-M. Chiu and J. C.-M. Li, “Ieee 1500 compatible secure test wrapper for embedded ip cores,” in 2008 IEEE International Test Conference . IEEE, 2008, pp. 1–1

    work page 2008

  41. [41]

    Test-mode-only scan attack and countermeasure for contemporary scan architectures,

    S. M. Saeed, S. S. Ali, O. Sinanoglu, and R. Karri, “Test-mode-only scan attack and countermeasure for contemporary scan architectures,” in 2014 International Test Conference . IEEE, 2014, pp. 1–8

    work page 2014

  42. [42]

    Effects of embedded decompression and compaction architectures on side-channel attack resistance

    C. Liu and Y . Huang, “Effects of embedded decompression and compaction architectures on side-channel attack resistance.” in VTS, 2007, pp. 461–468

    work page 2007

  43. [43]

    Are advanced dft structures sufficient for preventing scan-attacks?

    J. Da Rolt, G. Di Natale, M.-L. Flottes, and B. Rouzeyre, “Are advanced dft structures sufficient for preventing scan-attacks?” in 2012 IEEE 30th VLSI Test Symposium (VTS) . IEEE, 2012, pp. 246–251

    work page 2012

  44. [44]

    Scan attacks and countermeasures in presence of scan response compactors,

    J. DaRolt, G. Di Natale, M.-L. Flottes, and B. Rouzeyre, “Scan attacks and countermeasures in presence of scan response compactors,” in 2011 Sixteenth IEEE European Test Symposium . IEEE, 2011, pp. 19–24

    work page 2011

  45. [45]

    Scan chain encryption for the test, diagnosis and debug of secure circuits,

    M. Da Silva, M.-l. Flottes, G. Di Natale, B. Rouzeyre, P. Prinetto, and M. Restifo, “Scan chain encryption for the test, diagnosis and debug of secure circuits,” in 2017 22nd IEEE European Test Symposium (ETS) . IEEE, 2017, pp. 1–6

    work page 2017

  46. [46]

    Secured flipped scan-chain model for crypto-architecture,

    G. Sengar, D. Mukhopadhyay, and D. R. Chowdhury, “Secured flipped scan-chain model for crypto-architecture,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 26, no. 11, pp. 2080–2084, 2007

    work page 2080

  47. [47]

    Dynamically changeable secure scan architecture against scan-based side channel attack,

    Y . Atobe, Y . Shi, M. Yanagisawa, and N. Togawa, “Dynamically changeable secure scan architecture against scan-based side channel attack,” in 2012 International SoC Design Conference (ISOCC) . IEEE, 2012, pp. 155–158

    work page 2012

  48. [48]

    A low-cost solution for protecting ips against scan-based side-channel attacks,

    J. Lee, M. Tebranipoor, and J. Plusquellic, “A low-cost solution for protecting ips against scan-based side-channel attacks,” in 24th IEEE VLSI Test Symposium. IEEE, 2006, pp. 6–pp

    work page 2006

  49. [49]

    Sstkr: Secure and testable scan design through test key randomization,

    M. A. Razzaq, V . Singh, and A. Singh, “Sstkr: Secure and testable scan design through test key randomization,” in 2011 Asian Test Symposium. IEEE, 2011, pp. 60–65

    work page 2011

  50. [50]

    Vim-scan: A low overhead scan design approach for protection of secret key in scan-based secure chips,

    S. Paul, R. S. Chakraborty, and S. Bhunia, “Vim-scan: A low overhead scan design approach for protection of secret key in scan-based secure chips,” in 25th IEEE VLSI Test Symposium (VTS’07) . IEEE, 2007, pp. 455–460

    work page 2007

  51. [51]

    Secure scan and test using obfuscation throughout supply chain,

    X. Wang, D. Zhang, M. He, D. Su, and M. Tehranipoor, “Secure scan and test using obfuscation throughout supply chain,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 37, no. 9, pp. 1867–1880, 2017

    work page 2017

  52. [52]

    Scan design and secure chip

    D. Hely, M.-L. Flottes, F. Bancel, B. Rouzeyre, N. Berard, and M. Renovell, “Scan design and secure chip.” in IOLTS, vol. 4, 2004, pp. 219–224

    work page 2004

  53. [53]

    Securing designs against scan-based side-channel attacks,

    J. Lee, M. Tehranipoor, C. Patel, and J. Plusquellic, “Securing designs against scan-based side-channel attacks,” IEEE transactions on dependable and secure computing , vol. 4, no. 4, pp. 325–336, 2007

    work page 2007

  54. [54]

    Exploiting the scan side channel for reverse engineering of a vlsi device,

    L. Azriel, R. Ginosar, and A. Mendelson, “Exploiting the scan side channel for reverse engineering of a vlsi device,” Technion, Israel Institute of Technology, Tech. Rep. CCIT Report , vol. 897, 2016

    work page 2016

  55. [55]

    Protecting integrated circuits from piracy with test-aware logic locking,

    S. M. Plaza and I. L. Markov, “Protecting integrated circuits from piracy with test-aware logic locking,” in Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design . IEEE Press, 2014, pp. 262–269

    work page 2014

  56. [56]

    Provably-secure logic locking: From theory to practice,

    M. Yasin, A. Sengupta, M. T. Nabeel, M. Ashraf, J. J. Rajendran, and O. Sinanoglu, “Provably-secure logic locking: From theory to practice,” in Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security. ACM, 2017, pp. 1601–1618

    work page 2017

  57. [57]

    Novel bypass attack and bdd-based tradeoff analysis against all known logic locking attacks,

    X. Xu, B. Shakya, M. M. Tehranipoor, and D. Forte, “Novel bypass attack and bdd-based tradeoff analysis against all known logic locking attacks,” in International Conference on Cryptographic Hardware and Embedded Systems. Springer, 2017, pp. 189–210

    work page 2017

  58. [58]

    Functional analysis attacks on logic locking,

    D. Sirone and P. Subramanyan, “Functional analysis attacks on logic locking,” in 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019, pp. 936–939

    work page 2019

  59. [59]

    New scan-based attack using only the test mode,

    S. S. Ali, O. Sinanoglu, S. M. Saeed, and R. Karri, “New scan-based attack using only the test mode,” in 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) . IEEE, 2013, pp. 234–239

    work page 2013

  60. [60]

    Securing scan design using lock and key technique,

    J. Lee, M. Tehranipoor, C. Patel, and J. Plusquellic, “Securing scan design using lock and key technique,” in 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05) . IEEE, 2005, pp. 51–62

    work page 2005

  61. [61]

    Logic Locking for Secure Outsourced Chip Fabrication: A New Attack and Provably Secure Defense Mechanism

    M. E. Massad, J. Zhang, S. Garg, and M. V . Tripunitara, “Logic locking for secure outsourced chip fabrication: A new attack and provably secure defense mechanism,” arXiv preprint arXiv:1703.10187 , 2017

    work page internal anchor Pith review Pith/arXiv arXiv 2017

  62. [62]

    Sail: Machine learning guided structural analysis attack on hardware obfuscation,

    P. Chakraborty, J. Cruz, and S. Bhunia, “Sail: Machine learning guided structural analysis attack on hardware obfuscation,” in 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST). IEEE, 2018, pp. 56–61

    work page 2018

  63. [63]

    MicroNet Solutions, Inc

    “ MicroNet Solutions, Inc.” [Online]. Available: http://micronetsol.net/ pix2net-software/

    work page

  64. [64]

    Incremental sat-based reverse engineering of camouflaged logic circuits,

    C. Yu, X. Zhang, D. Liu, M. Ciesielski, and D. Holcomb, “Incremental sat-based reverse engineering of camouflaged logic circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 10, pp. 1647–1659, 2017

    work page 2017

  65. [65]

    Trojan side-channels: lightweight hardware trojans through side-channel engineering,

    L. Lin, M. Kasper, T. G ¨uneysu, C. Paar, and W. Burleson, “Trojan side-channels: lightweight hardware trojans through side-channel engineering,” in International Workshop on Cryptographic Hardware and Embedded Systems . Springer, 2009, pp. 382–395

    work page 2009

  66. [66]

    Chip design in china and india: Multinationals, industry structure and development outcomes in the integrated circuit industry,

    D. B. Fuller, “Chip design in china and india: Multinationals, industry structure and development outcomes in the integrated circuit industry,” Technological Forecasting and Social Change, vol. 81, pp. 1–10, 2014

    work page 2014

  67. [67]

    Physical inspection & attacks: New frontier in hardware security,

    M. T. Rahman, Q. Shi, S. Tajik, H. Shen, D. L. Woodard, M. Tehranipoor, and N. Asadizanjani, “Physical inspection & attacks: New frontier in hardware security,” in 2018 IEEE 3rd International Verification and Security Workshop (IVSW) . IEEE, 2018, pp. 93–102

    work page 2018

  68. [68]

    A survey of hardware trojan taxonomy and detection,

    M. Tehranipoor and F. Koushanfar, “A survey of hardware trojan taxonomy and detection,” IEEE design & test of computers , vol. 27, no. 1, 2010

    work page 2010

  69. [69]

    Trojan scanner: Detecting hardware trojans with rapid sem imaging combined with image processing and machine learning,

    N. Vashistha, H. Lu, Q. Shi, M. T. Rahman, H. Shen, D. L. Woodard, N. Asadizanjani, and M. Tehranipoor, “Trojan scanner: Detecting hardware trojans with rapid sem imaging combined with image processing and machine learning,” in ISTFA 2018: Proceedings from the 44th International Symposium for Testing and Failure Analysis. ASM International, 2018, p. 256

    work page 2018

  70. [70]

    Golden gates: A new hybrid approach for rapid hardware trojan detection using testing and imaging,

    Q. Shi, N. Vashistha, H. Lu, H. Shen, B. Tehranipoor, D. L. Woodard, and N. Asadizanjani, “Golden gates: A new hybrid approach for rapid hardware trojan detection using testing and imaging,” in 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2019, pp. 61–71

    work page 2019

  71. [71]

    Threshold-based obfuscated keys with quantifiable security against invasive readout,

    S. Keshavarz and D. Holcomb, “Threshold-based obfuscated keys with quantifiable security against invasive readout,” in Proceedings of the 36th International Conference on Computer-Aided Design. IEEE Press, 2017, pp. 57–64

    work page 2017

  72. [72]

    A logic resistive memory chip for embedded key storage with physical security,

    Y . Xie, X. Xue, J. Yang, Y . Lin, Q. Zou, R. Huang, and J. Wu, “A logic resistive memory chip for embedded key storage with physical security,” IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 63, no. 4, pp. 336–340, 2016

    work page 2016

  73. [73]

    Cross-lock: Dense layout-level interconnect locking using cross-bar architectures,

    K. Shamsi, M. Li, D. Z. Pan, and Y . Jin, “Cross-lock: Dense layout-level interconnect locking using cross-bar architectures,” in Proceedings of the 2018 on Great Lakes Symposium on VLSI . ACM, 2018, pp. 147–152

    work page 2018

  74. [74]

    A secure camouflaged threshold voltage defined logic family,

    B. Erbagci, C. Erbagci, N. E. C. Akkaya, and K. Mai, “A secure camouflaged threshold voltage defined logic family,” in 2016 IEEE International symposium on hardware oriented security and trust (HOST). IEEE, 2016, pp. 229–235

    work page 2016

  75. [75]

    A secure camouflaged logic family using post-manufacturing programming with a 3.6 ghz adder prototype in 65nm cmos at 1v nominal v dd,

    N. E. C. Akkaya, B. Erbagci, and K. Mai, “A secure camouflaged logic family using post-manufacturing programming with a 3.6 ghz adder prototype in 65nm cmos at 1v nominal v dd,” in2018 IEEE International Solid-State Circuits Conference-(ISSCC) . IEEE, 2018, pp. 128–130

    work page 2018

  76. [76]

    Nanopyramid: An optical scrambler against backside probing attacks,

    H. Shen, N. Asadizanjani, M. Tehranipoor, and D. Forte, “Nanopyramid: An optical scrambler against backside probing attacks,” in ISTFA 2018: Proceedings from the 44th International Symposium for Testing and Failure Analysis. ASM International, 2018, p. 280

    work page 2018

  77. [77]

    Backside polishing detector: a new protection against backside attacks,

    S. Manich Bou, D. Arumi Delgado, R. Rodr ´ıguez Monta ˜n´es, J. Mujal Colell, and D. Hern ´andez Garc´ıa, “Backside polishing detector: a new protection against backside attacks,” in DCIS’15-XXX Conference on Design of Circuits and Integrated Systems , 2015

    work page 2015

  78. [78]

    Assessment of a chip backside protection,

    E. Amini, A. Beyreuther, N. Herfurth, A. Steigert, B. Szyszka, and C. Boit, “Assessment of a chip backside protection,” Journal of Hardware and Systems Security , vol. 2, no. 4, pp. 345–352, 2018

    work page 2018

  79. [79]

    Pufmon: Security monitoring of fpgas using physically unclonable functions,

    S. Tajik, J. Fietkau, H. Lohrke, J.-P. Seifert, and C. Boit, “Pufmon: Security monitoring of fpgas using physically unclonable functions,” in 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS) . IEEE, 2017, pp. 186–191

    work page 2017

  80. [80]

    A novel structure for backside protection against physical attacks on secure chips or sip,

    S. Borel, L. Duperrex, E. Deschaseaux, J. Charbonnier, J. Cledi `ere, R. Wacquez, J. Fournier, J.-C. Souriau, G. Simon, and A. Merle, “A novel structure for backside protection against physical attacks on secure chips or sip,” in 2018 IEEE 68th Electronic Components and Technology Conference (ECTC). IEEE, 2018, pp. 515–520. 21

    work page 2018

Showing first 80 references.