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arxiv: 1908.04718 · v1 · pith:64VGPZTRnew · submitted 2019-08-13 · 💻 cs.DB · cs.PF

Micro-architectural Analysis of OLAP: Limitations and Opportunities

Utku Sirin , Anastasia Ailamaki This is my paper

Pith reviewed 2026-05-24 16:20 UTC · model grok-4.3

classification 💻 cs.DB cs.PF
keywords OLAPmicro-architectural analysisCPU stallsmemory bandwidth utilizationcolumn storesperformance countersanalytical workloadsinstruction footprint
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The pith

High-performance OLAP engines spend 25 to 82 percent of CPU cycles on stalls and underutilize multi-core CPUs and memory bandwidth due to mismatched compute and memory demands.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper measures how modern OLAP systems behave at the level of CPU cycles, stalls, and memory bandwidth on contemporary hardware. Unlike OLTP systems, these analytical engines avoid instruction cache misses but still carry large instruction footprints that lengthen response times. Even tightly optimized column-store engines lose a quarter to more than three-quarters of their cycles to stalls, whether the queries touch data sequentially or randomly. The engines also fail to saturate available cores or memory bandwidth because their compute and memory requirements stay out of proportion. A reader would care because the measurements identify concrete hardware-level limits that any redesign of analytical engines must address.

Core claim

Traditional commercial OLAP systems exhibit large instruction footprints that slow response times yet do not suffer instruction cache misses. High-performance OLAP engines run tight instruction streams but still spend 25 to 82 percent of CPU cycles on stalls across both sequential- and random-access workloads. These same engines underutilize multi-core CPU resources and memory bandwidth because their compute and memory demands remain disproportional.

What carries the argument

Hardware performance counter measurements of CPU cycle breakdown, stall sources, and memory bandwidth utilization across multiple OLAP systems and query patterns.

If this is right

  • Analytical engines must deliberately balance compute and memory resource assignment to achieve efficient multi-core utilization.
  • Reducing stall cycles remains necessary even for engines that already use compact instruction streams.
  • Workload access pattern (sequential versus random) does not alter the high stall percentage observed.
  • Large instruction footprints in commercial OLAP systems continue to limit response times despite the absence of cache misses.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Designers of future column stores could explore tighter integration of compute and memory scheduling to close the observed utilization gap.
  • The same measurement approach could be applied to emerging hardware such as persistent memory or accelerators to check whether the stall and bandwidth patterns persist.
  • Query optimizers might incorporate stall and bandwidth models as cost factors once the disproportional demand pattern is confirmed across more systems.

Load-bearing premise

The specific OLAP systems, queries, and data sets measured are representative of production analytical workloads and the performance counters accurately reflect dominant bottlenecks.

What would settle it

Repeating the measurements on additional production OLAP engines or workloads that consistently show stall fractions below 25 percent or near-full memory bandwidth utilization would falsify the central claim.

Figures

Figures reproduced from arXiv: 1908.04718 by Anastasia Ailamaki, Utku Sirin.

Figure 1
Figure 1. Figure 1: CPU cycles breakdown for projection as projectivity increases for DBMS R and DBMS C. 1 Projectivity 0% 20% 40% 60% 80% 100% p1 p2 p3 p4 p1 p2 p3 p4 DBMS R DBMS C CPU cycles (%) Projectivity Stall Retiring 0% 20% 40% 60% 80% 100% p1 p2 p3 p4 p1 p2 p3 p4 DBMS R DBMS C Stall cycles (%) Projectivity Execution Dcache Decoding Icache Branch misp. 0% 20% 40% 60% 80% 100% p1 p2 p3 p4 p1 p2 p3 p4 Typer Tectorwise C… view at source ↗
Figure 5
Figure 5. Figure 5: Single-core sequential access bandwidth DBMS R DBMS C Typer Tectorwise [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 9
Figure 9. Figure 9: shows the CPU cycles breakdown for Typer and Tectorwise. Unlike DBMS R and C, Typer and Tectorwise have the highest stall cycles ratio at 50% [PITH_FULL_IMAGE:figures/full_fig_p005_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: CPU cycles breakdown for join for Join size [PITH_FULL_IMAGE:figures/full_fig_p006_11.png] view at source ↗
Figure 15
Figure 15. Figure 15: shows the CPU cycles breakdown. As can be seen, both Typer and Tectorwise have the highest Retiring cycles ratio when running Q1. Whereas Typer has the lowest Retiring cycles ratio when running Q9, and Tectorwise has the lowest Retiring cycles ratio when running Q6 [PITH_FULL_IMAGE:figures/full_fig_p007_15.png] view at source ↗
Figure 19
Figure 19. Figure 19: Response time breakdown for Tector Selectivity [PITH_FULL_IMAGE:figures/full_fig_p008_19.png] view at source ↗
Figure 21
Figure 21. Figure 21: Single-core bandwidth utilization for 1 me [PITH_FULL_IMAGE:figures/full_fig_p009_21.png] view at source ↗
Figure 23
Figure 23. Figure 23: Normalized stall time breakdown for Tectorwise when running projection and selection queries with and without SIMD [PITH_FULL_IMAGE:figures/full_fig_p009_23.png] view at source ↗
Figure 25
Figure 25. Figure 25: (left) shows the normalized response time break￾down, where the response time without SIMD is taken as the base. Note that the response time breakdown includes the stall time breakdown inside on the same graph [PITH_FULL_IMAGE:figures/full_fig_p010_25.png] view at source ↗
Figure 26
Figure 26. Figure 26: Response time breakdown for the six prefetcher configuration for Typer when running the projection micro-benchmark with degree of four [PITH_FULL_IMAGE:figures/full_fig_p010_26.png] view at source ↗
Figure 27
Figure 27. Figure 27: and 28 show the CPU and stall cycles break￾downs. As can be seen, both CPU and stall cycles break￾downs are similar to the single-core breakdowns. While the low-cardinality group by Q1 has the highest Retiring cy￾cles ratio both for Typer and Tectorwise, join-intensive Q9 has the lowest Retiring cycles ratio for Typer, and highly selective filter Q6 has the lowest Retiring cycles ratio for Tectorwise. Whi… view at source ↗
Figure 29
Figure 29. Figure 29: Multi-core bandwidth utilization for Typer and Tectorwise when running the projection query with degree of four. Tectorwise can be improved by using hyper-threading. Our analysis with hyper-threading showed that the bandwidth utilization is improved by 1.3x both for Typer and Tec￾torwise. Hence, Tectorwise’s (together with SIMD) and Typer’s bandwidth utilizations would raise up to 40 GB/s and 27 GB/s when… view at source ↗
read the original abstract

Understanding micro-architectural behavior is profound in efficiently using hardware resources. Recent work has shown that, despite being aggressively optimized for modern hardware, in-memory online transaction processing (OLTP) systems severely underutilize their core micro-architecture resources [25]. Online analytical processing (OLAP) workloads, on the other hand, exhibit a completely different computing pattern. OLAP workloads are read-only, bandwidth-intensive and include various data access patterns including both sequential and random data accesses. In addition, with the rise of column-stores, they run on high performance engines that are tightly optimized for the efficient use of modern hardware. Hence, the micro-architectural behavior of modern OLAP systems remains unclear. This work presents the micro-architectural analysis of a breadth of OLAP systems. We examine CPU cycles and memory bandwidth utilization. The results show that, unlike the traditional, commercial OLTP systems, traditional, commercial OLAP systems do not suffer from instruction cache misses. Nevertheless, they suffer from their large instruction footprint resulting in slow response times. High performance OLAP engines execute tight instruction streams; however, they spend 25 to 82% of the CPU cycles on stalls regardless of the workload being sequential- or random-access-heavy. In addition, high performance OLAP engines underutilize the multi-core CPU or memory bandwidth resources due to their disproportional compute and memory demands. Hence, analytical processing engines should carefully assign their compute and memory resources for efficient multi-core micro-architectural utilization.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper presents an empirical micro-architectural analysis of multiple OLAP systems using hardware performance counters to measure CPU cycle stalls and memory bandwidth utilization. It claims that, unlike OLTP systems, OLAP engines do not suffer from instruction cache misses but incur slow response times from large instruction footprints; high-performance OLAP engines spend 25-82% of CPU cycles on stalls irrespective of sequential or random access patterns and underutilize multi-core CPUs and memory bandwidth due to disproportional compute and memory demands, recommending careful resource assignment for analytical engines.

Significance. If the measurements generalize, the work supplies concrete quantitative evidence of substantial resource underutilization in modern column-store OLAP engines, identifying opportunities for hardware-software co-design improvements in bandwidth-intensive analytical workloads. The direct use of hardware counters yields falsifiable stall-fraction observations that could guide future engine optimizations.

major comments (2)
  1. [Experimental Setup / Workload Selection] The central claim of a 25-82% stall range 'regardless of the workload being sequential- or random-access-heavy' (abstract) rests on the representativeness of the chosen OLAP engines, queries, and datasets. The experimental corpus must be shown to capture production instruction footprints, cache behavior, and bandwidth/compute balance; otherwise the attribution to 'disproportional compute and memory demands' does not necessarily extend beyond the measured instances.
  2. [Results / Quantitative Observations] No error bars, standard deviations, raw counter values, or repeated-run statistics accompany the reported stall fractions and utilization numbers (abstract and results). This absence prevents verification that the observed ranges are robust to measurement overhead, configuration artifacts, or post-hoc workload selection.
minor comments (2)
  1. [Abstract and Introduction] Clarify the distinction between 'traditional, commercial OLAP systems' and 'high performance OLAP engines' throughout the text to avoid ambiguity in the contrast with OLTP.
  2. [Methodology] Provide explicit definitions or references for the hardware performance counter events used to classify stalls and bandwidth utilization.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our empirical analysis of OLAP micro-architectural behavior. We address each major comment below, indicating planned revisions where appropriate.

read point-by-point responses

  1. Referee: [Experimental Setup / Workload Selection] The central claim of a 25-82% stall range 'regardless of the workload being sequential- or random-access-heavy' (abstract) rests on the representativeness of the chosen OLAP engines, queries, and datasets. The experimental corpus must be shown to capture production instruction footprints, cache behavior, and bandwidth/compute balance; otherwise the attribution to 'disproportional compute and memory demands' does not necessarily extend beyond the measured instances.

    Authors: Our experiments cover multiple OLAP engines (both traditional row-stores and high-performance column-stores) and standard analytical benchmarks (TPC-H and Star Schema Benchmark) chosen specifically to include both sequential scan-heavy and random access patterns. These benchmarks are widely accepted as representative of production analytical workloads in the database literature. We will revise the manuscript to add an expanded discussion of workload selection criteria, including how the chosen queries exercise instruction footprints and cache behavior observed in the measured stall ranges. Direct reproduction of proprietary production traces is not possible, but the observed 25-82% stall range holds consistently across the selected corpus. revision: partial

  2. Referee: [Results / Quantitative Observations] No error bars, standard deviations, raw counter values, or repeated-run statistics accompany the reported stall fractions and utilization numbers (abstract and results). This absence prevents verification that the observed ranges are robust to measurement overhead, configuration artifacts, or post-hoc workload selection.

    Authors: We agree that the absence of statistical measures limits verifiability. Hardware counter readings were collected over repeated executions with stable system configurations to mitigate measurement artifacts, yet variance was not reported. In the revised version we will add error bars, standard deviations from multiple runs, and representative raw counter values for the key stall and bandwidth metrics to demonstrate robustness of the reported ranges. revision: yes

Circularity Check

0 steps flagged

Empirical measurement study; no derivation chain or self-referential reduction

full rationale

The paper reports direct hardware-counter observations (stall fractions 25-82%, bandwidth/CPU underutilization) on chosen OLAP engines and workloads. No equations, fitted parameters, or predictions are defined in terms of the reported quantities. The single citation to prior OLTP work [25] is external contrast, not load-bearing for the OLAP measurements. The work is self-contained against external benchmarks (hardware counters on specific systems) and does not reduce any result to its own inputs by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The analysis rests on the assumption that the chosen commercial and high-performance OLAP engines plus the tested query mix are representative; no free parameters, mathematical axioms, or invented entities are introduced because the contribution is observational profiling rather than modeling.

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discussion (0)

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Reference graph

Works this paper leans on

46 extracted references · 46 canonical work pages · 1 internal anchor

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