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REVIEW 3 major objections 6 minor 48 references

FLASH-FHE: A Heterogeneous Architecture for Fully Homomorphic Encryption Acceleration

T0 review · 3 major / 6 minor · reviewed 2026-08-09 · deepseek-v4-flash

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Pith's one-line read FLASH-FHE is presented as the first FHE accelerator with a heterogeneous architecture, pairing bootstrappable clusters for deep workloads with swift clusters that run shallow workloads in parallel.

desk verdict A genuinely new heterogeneous FHE architecture with a clever multi-exit NTT design, but the 8x shallow speedup is not convincingly attributed to heterogeneity because the baseline's multi-job capability is never analyzed. read the letter →

arxiv 2501.18371 v1 pith:AXC6FM47 submitted 2025-01-30 cs.AR cs.CR

Junxue Zhang , Xiaodian Cheng , Gang Cao , Meng Dai , Yijun Sun , Han Tian , Dian Shen , Yong Wang
show 1 more author
Kai Chen
This is my paper · ORCID
classification cs.ARcs.CR
keywords FHEacceleratorheterogeneousarchitecturebootstrappingNTTpipelinemulti-jobschedulingshallowworkloadsdeephardware
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Real fully homomorphic encryption (FHE) workloads mix shallow computations, which can run without bootstrapping, and deep computations, which need the expensive bootstrapping refresh; existing accelerators optimize for only one of the two. FLASH-FHE's claim is that a single heterogeneous chip can serve both: it pairs large bootstrappable clusters with smaller swift clusters, and schedules deep jobs across all clusters while running up to eight shallow jobs in parallel. The paper reports average speedups of 1.4x over CraterLake and 11.2x over F1+ on deep workloads, and up to 8.0x on shallow workloads, with the swift engines costing under 7% extra chip area. If the design holds up, FHE acceleration no longer has to force a choice between deep capacity and shallow throughput.

What carries the argument

The central mechanism is the cluster affiliation: one bootstrappable cluster paired with two swift clusters, repeated eight times. The bootstrappable cluster is a pipelined NTT/iNTT-BConv-NTT engine for $N=2^{16}$; the swift clusters are $N=2^{14}$ NTT engines. Multi-level transpose hardware (L1/L2/L3) and explicit NTT entrance and exit points let a single large NTT circuit be split into multiple small parallel NTTs, so the same physical datapath accelerates both deep and shallow workloads. The scheduler then either distributes one deep job over all eight bootstrappable clusters or assigns one shallow job to each affiliation, while shared L1/L2 caches keep the shallow engines from duplicating memory.

What would settle it

If a multi-job scheduler added to a homogeneous accelerator with eight bootstrapping computation groups yields nearly the same shallow-workload throughput as FLASH-FHE on the same benchmarks at the same technology node, then the central heterogeneity claim is falsified.

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Extended reading notes

Core claim

The paper's central claim is that heterogeneity, not more homogeneous compute, is the missing ingredient for mixed FHE workloads. The chip is organized into eight cluster affiliations, each with one bootstrappable cluster built around a $2^{16}$-point NTT-to-BConv-to-NTT pipeline and two swift clusters with $2^{14}$-point NTT pipelines. Deep workloads engage all bootstrappable clusters; shallow workloads are assigned one per affiliation, and the bootstrappable NTT is dynamically decomposed into smaller parallel NTT pipelines to add throughput. A multi-level transpose and shared hierarchical cache keep the added parallelism cheap. As a result the paper reports 1.4x and 11.2x average deep-workload gains over CraterLake and F1+, and up to 8.0x shallow-workload gains, at under 7% extra area for the swift cluster logic.

Load-bearing premise

The load-bearing premise is that a homogeneous accelerator like CraterLake cannot be given a multi-job scheduling policy and therefore must process shallow workloads sequentially, so the up-to-8x shallow gain is really caused by heterogeneous hardware rather than by a scheduler that could have been added to the existing homogeneous design.

Editorial extensions

If this is right

  • Deep FHE workloads gain an average 1.4x over CraterLake and 11.2x over F1+ across packed bootstrapping, ResNet-20, logistic regression, and LSTM.
  • Shallow FHE workloads can be processed up to eight in parallel, reaching up to 8.0x throughput when enough independent shallow jobs are present.
  • The added swift cluster logic costs less than 7% of total chip area, since the swift and bootstrappable clusters share on-chip L1/L2 caches.
  • At the 7nm node FLASH-FHE delivers 1.49x to 1.78x better performance per area than ARK on the two compared deep workloads, while SHARP's short-word optimization remains faster in absolute terms.
  • The heterogeneous organization can be layered onto existing deep-workload accelerators by adding multi-exit NTT pipelines, a multi-level transpose, and the multi-job scheduler.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The one-bootstrappable-to-two-swift ratio is dictated by NTT circuit geometry (a $2^8$ versus $2^7$ radix), not by measured deep-to-shallow workload mix; a deployment dominated by shallow jobs might want a different ratio, a tradeoff the paper does not explore.
  • The 8x shallow speedup fundamentally depends on having at least several shallow jobs in flight at once; under sparse or bursty job arrivals, queueing and preemption policy, not peak throughput, will determine the realized gain.
  • The same multi-exit NTT decomposition idea could be used to time-share a single large NTT datapath across job sizes even in a homogeneous chip, suggesting part of the benefit may be obtainable without the second cluster type.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. FLASH-FHE proposes a heterogeneous FHE accelerator that combines eight 'bootstrappable' clusters (optimized for deep workloads with 2^16-point NTT and BConv pipelines) and sixteen 'swift' clusters (optimized for shallow workloads with 2^14-point NTT pipelines), organized into eight cluster affiliations. A scheduling scheme assigns one shallow workload per affiliation and decomposes the bootstrappable cluster into multiple small-point NTT pipelines, while deep workloads use all bootstrappable clusters jointly. The paper reports an RTL implementation synthesized at 7nm and 14/12nm, a cycle-accurate simulator evaluation on seven workloads, a 1.4x average deep-workload speedup over CraterLake, an 11.2x speedup over F1+, and up to 8.0x shallow-workload speedup attributed to the heterogeneous architecture, with less than 7% extra chip area for the swift engines.

Significance. If the architectural claims are substantiated, this is a useful and timely contribution: it is among the first FHE accelerator designs to explicitly target mixed shallow/deep workloads, and it provides a concrete heterogeneous organization with full RTL, synthesis results at two technology nodes, area/power breakdowns, and a stated path for integrating the ideas into existing accelerators such as CraterLake, ARK, and SHARP. The paper also names its limitations honestly, including the lack of support for combining swift clusters for deep workloads (Section 7) and the disclosure that the deep-workload advantage over CraterLake comes mainly from the larger 320MB cache rather than from heterogeneity (Section 6.3). The main unresolved issue is whether the headline 8x shallow-workload speedup is genuinely caused by the heterogeneous design or is instead a batch-parallelism effect that a homogeneous multi-group accelerator could also achieve under a different scheduler.

major comments (3)
  1. [§3.3, §6.3 (Fig. 12)] The central claim that the up-to-8.0x shallow-workload speedup is 'due to its heterogeneous architecture' is not yet established. The paper asserts in §3.3 that existing accelerators 'can only handle one job simultaneously' and in §6.3 that CraterLake 'can only use a sequential scheduling policy due to its homogeneous design,' but no architectural or software-stack analysis is provided to rule out a multi-job scheduler for CraterLake. Since CraterLake already contains eight computation groups with independent 256-lane NTT engines and local register files, a batch scheduler assigning one shallow job per group could plausibly capture most of the same throughput gain; in that case the 8x figure reflects parallelism available to any multi-group accelerator, not the heterogeneous design. Please add a fair CraterLake scheduler to the simulation, or provide a structural proof that CraterLake's hardware and software stack cannot support multi-job execution.
  2. [§4.1 (Fig. 4), §4.2] The key mechanism of dynamically decomposing a 2^16-point (i)NTT pipeline into multiple smaller pipelines via multi-entry/multi-exit ports is assumed to be throughput-preserving with negligible overhead, but no microbenchmark or area/latency analysis isolates this effect. The shallow-workload speedup depends directly on the throughput of a bootstrappable cluster in decomposed mode, so the paper should report the effective NTT throughput (or lack of throughput loss) for the decomposed configuration and quantify the added mux/delay logic in the synthesized area.
  3. [§6.3 (Fig. 9)] The single-workload shallow comparison is not apples-to-apples: FLASH-FHE uses L=6 for the LoLa-MNIST variants while CraterLake and F1+ use L=4, and the paper acknowledges that FLASH-FHE is slower in these settings. The subsequent multi-workload claim should therefore be stated as a comparison of batch throughput under a fixed (larger) parameter set, not as a general shallow-workload speedup; otherwise the headline 8x result conflates parameter choice with architectural benefit.
minor comments (6)
  1. [Abstract, §1, §6.1] The abstract and introduction refer to 'F1' while the evaluation compares against 'F1+'; please use consistent naming throughout.
  2. [Title] The title contains an unexplained typographical artifact '/b♀t'; if this is intended to evoke big.LITTLE, please spell it out in words.
  3. [§6.3] The phrase 'speedup of 0.4–2.2x' is a slowdown at the lower end; please describe these results as relative performance ratios rather than speedups when the ratio is below 1.
  4. [§4.2, Table 3] The statement that the swift clusters consume less than 7% of chip area refers ahead to Table 3; please cite the table directly and clarify whether this is logic-only area, since the swift clusters share L1/L2 memory.
  5. [§6.1] The evaluation methodology would be strengthened by a short description of the cycle-accurate simulator's memory model, including HBM bandwidth and memory-controller contention, since the performance comparisons rely on it.
  6. [Figure 2] Figure 2 lacks a caption in the manuscript text; please add one that clearly states that diminishing returns set in above four cooperating computation clusters, since this observation drives the motivation for parallel shallow-workload scheduling.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found; the headline speedups are architectural throughput results evaluated against external baselines, not self-referential derivations.

full rationale

The paper does not fit parameters to target results and then report them as predictions, nor does any claimed derivation reduce to its own inputs by construction. The central design—heterogeneous bootstrappable and swift clusters organized into eight cluster affiliations, with a scheduler that assigns one shallow workload per affiliation—is implemented in RTL and evaluated against external accelerators (CraterLake, F1+, ARK, SHARP) using reported data from those papers. The up-to-8x shallow-workload speedup is a direct throughput consequence of running up to eight shallow jobs concurrently across eight cluster affiliations; it is a capacity and scheduling claim, not a circular restatement of the architecture's definition. The 1.4x deep-workload improvement over CraterLake is attributed to a larger 320MB cache versus 256MB, which is an externally checkable design choice rather than a fitted constant. Self-citations, specifically the authors' prior FLASH and SoK works (references [46] and [47]), appear only in background and related-work discussion and are not load-bearing for the paper's central claims. The weakest point is the asserted premise that CraterLake's homogeneous design forces a sequential single-job scheduling policy; the paper does not prove that CraterLake's eight computation groups could not execute multiple shallow jobs under a different scheduler. If that premise is false, the 8x comparison would overstate the benefit of heterogeneity, but this is a correctness or experimental-design risk about baseline capability, not circularity under the defined patterns. No self-definitional step, fitted-input-called-prediction, load-bearing self-citation, imported uniqueness theorem, smuggled ansatz, or renamed known result is present in the derivation chain.

Assumptions & free parameters 5 free parameters · 4 assumptions · 0 invented entities

The paper introduces no new physical or formal entities; the bootstrappable and swift clusters are designed hardware modules with specified RTL, not unexplained postulates. The main load-bearing choices are architectural parameters (cache size, cluster counts, affiliation ratio) and modeling assumptions about baseline accelerators.

free parameters (5)
  • L2 cache capacity = 320 MB
    Chosen from a sweep of total cache volume (Figure 8) to maximize key-switching speedup for dnum=1,2,3. The deep-workload speedup over CraterLake is attributed to this cache, so the number is load-bearing for the 1.4x claim.
  • BConv parallel lanes lsub = 60
    Hand-picked to maximize BConv throughput in the key-switching pipeline; affects area and deep workload performance.
  • Number of cluster affiliations = 8
    Architectural choice; the shallow-workload 8.0x speedup is essentially the number of affiliations times per-affiliation parallelism.
  • Bootstrappable-to-swift cluster ratio = 1:2
    Chosen mainly to match the 2^8-point vs 2^7-point NTT circuit sizes for transpose sharing, not derived from workload ratios.
  • Shallow workload level L in FLASH-FHE vs baselines = L=6 vs L=4
    The paper reports single-workload shallow results with L=6 for FLASH-FHE and L=4 for F1 and CraterLake; this parameter difference affects the comparison and is acknowledged in Section 6.3.
assumptions (4)
  • domain assumption The cycle-accurate simulator models FLASH-FHE and baseline accelerators faithfully, and baseline performance numbers from prior papers are correct.
    Invoked in Section 6.1; no simulator or baseline code is released, so the validity of all speedup numbers depends on this.
  • domain assumption Existing homogeneous accelerators such as CraterLake cannot execute multiple shallow FHE workloads in parallel, so multi-job throughput is unique to FLASH-FHE.
    Stated in Sections 3.3 and 6.3 without hardware or scheduler analysis showing a fundamental limitation.
  • ad hoc to paper Decomposing a 2^16-point (i)NTT pipeline into multiple smaller (i)NTT pipelines via multi-entry and multi-exit ports has negligible overhead and preserves throughput.
    Assumed in Section 4.1 to justify the swift and decomposed modes; no standalone benchmark compares decomposed vs monolithic NTT at equal throughput.
  • standard math NTT, iNTT, RNS decomposition, basis conversion, and CKKS/BGV/BFV correctness follow from cited prior work.
    Background from Sections 2.1 and 2.2; not re-derived in this paper.

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Cite this review

Pith. "Pith review of FLASH-FHE: A Heterogeneous Architecture for Fully Homomorphic Encryption Acceleration." pith.science (2026). https://pith.science/paper/AXC6FM47

@misc{pith2026250118371,
  author       = {Pith},
  title        = {Pith review of: FLASH-FHE: A Heterogeneous Architecture for Fully Homomorphic Encryption Acceleration},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/AXC6FM47}},
  note         = {Machine review of arXiv:2501.18371}
}
abstract

While many hardware accelerators have recently been proposed to address the inefficiency problem of fully homomorphic encryption (FHE) schemes, none of them is able to deliver optimal performance when facing real-world FHE workloads consisting of a mixture of shallow and deep computations, due primarily to their homogeneous design principle. This paper presents FLASH-FHE, the first FHE accelerator with a heterogeneous architecture for mixed workloads. At its heart, FLASH-FHE designs two types of computation clusters, ie, bootstrappable and swift, to optimize for deep and shallow workloads respectively in terms of cryptographic parameters and hardware pipelines. We organize one bootstrappable and two swift clusters into one cluster affiliation, and present a scheduling scheme that provides sufficient acceleration for deep FHE workloads by utilizing all the affiliations, while improving parallelism for shallow FHE workloads by assigning one shallow workload per affiliation and dynamically decomposing the bootstrappable cluster into multiple swift pipelines to accelerate the assigned workload. We further show that these two types of clusters can share valuable on-chip memory, improving performance without significant resource consumption. We implement FLASH-FHE with RTL and synthesize it using both 7nm and 14/12nm technology nodes, and our experiment results demonstrate that FLASH-FHE achieves an average performance improvement of $1.4\times$ and $11.2\times$ compared to state-of-the-art FHE accelerators CraterLake and F1 for deep workloads, while delivering up to $8.0\times$ speedup for shallow workloads due to its heterogeneous architecture.

Figures

Figures reproduced from arXiv: 2501.18371 by the authors.

Figure 1
Figure 1. Performance of FHE Workloads. samples per batch. We perform bootstrapping once the multiplication level is exhausted. • LSTM: Long Short-Term Memory (LSTM) is a recurrent neural network (RNN), which is widely adopted to learn the long-term dependencies, especially in sequence prediction problems. In this paper, we follow the implementation in [36] to use CKKS to protected the parameters of a LSTM network. It’s also … view at source ↗
Figure 3
Figure 3. FLASH-FHE’s architectural overview. 4 FLASH-FHE To solve this problem, we propose FLASH-FHE, a practical FHE accelerator with a heterogeneous architecture. Instead of relying on homogeneous computation clusters, FLASH-FHE incorporates two types of clusters: bootstrappable and swift. In terms of cryptographic parameters and pipeline design, these clusters are optimized for deep and shallow workloads, respectively. We… view at source ↗
Figure 4
Figure 4. (i)NTT workflow. The (i)NTT pipeline in FLASH-FHE supports multiple entrances and multiple exits to enable efficient execution of varying-point NTTs. Bootstrappable Clusters: To ensure efficient bootstrapping, we implement a complete iNTT → BConv → NTT pipeline for bootstrappable clusters, following previous works [28– 30, 41]. Within a bootstrappable cluster, we incorporate one (i)NTT pipeline and one BConv module.… view at source ↗
Figures from the paper (6 more)
Figure 5
Figure 5. Figure 5: The physical design of the bootstrappable computa [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 7
Figure 7. Figure 7: Unified building block of L1 transpose module. [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: Performance of key-switching over varying cache [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]
Figure 10
Figure 10. Figure 10: [7nm Technology Node] Performance of FLASH-FHE. in [PITH_FULL_IMAGE:figures/full_fig_p012_10.png]
Figure 11
Figure 11. Figure 11: Performance of FLASH-FHE compared to represen￾tative GPU and FPGA solutions. is orthogonal to the optimizations used in ARK and SHARP. Therefore, we can combine FLASH-FHE with them to further improve their performance for mixed FHE workloads. Multiple Shallow Workload…
Figure 13
Figure 13. Figure 13: Power consumption breakdown. workloads. 6.4 Power Consumption We also conducted an evaluation of the power consump￾tion of FLASH-FHE using the 14/12nm technology node, as we currently lack access to the power budget for cer￾tain logic modules in the 7nm technology. Th…

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Pith tools

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