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arxiv: 2503.09676 · v3 · pith:S3UL3QXMnew · submitted 2025-03-12 · 🧮 math.OC · cs.AR

Hardware-Compatible Single-Shot Feasible-Space Heuristics for Solving the Quadratic Assignment Problem

Haesol Im , Chan-Woo Yang , Moslem Noori , Dmitrii Dobrynin , Elisabetta Valiante , Giacomo Pedretti , Arne Heittmann , Thomas Van Vaerenbergh
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Masoud Mohseni John Paul Strachan Dmitri Strukov Ray Beausoleil Ignacio Rozada
This is my paper

Pith reviewed 2026-05-22 23:47 UTC · model grok-4.3

classification 🧮 math.OC cs.AR
keywords quadratic assignment problemfeasible-space heuristicin-memory computinglocal searchhardware-aware optimizationcombinatorial optimizationparallel neighborhood evaluation
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The pith

Co-designing local search with hardware allows single-shot evaluation of full feasible neighborhoods for the quadratic assignment problem.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a hardware-aware optimization framework for the quadratic assignment problem that works on in-memory computing devices. It co-designs the local search so that the full set of feasible neighboring solutions can be evaluated together in one parallel step, then picks only the moves that keep the solution feasible. This sidesteps the usual overhead of turning constrained problems into unconstrained binary forms. A reader would care because the method runs on both ordinary CPUs and specialized analog hardware while staying competitive with existing heuristics.

Core claim

By co-designing the local search heuristic with the underlying hardware, full neighbourhoods can be computed simultaneously to make update decisions. Binary solutions remain feasible by selecting local moves that lead to neighbouring feasible solutions. The approach is compatible with both digital computers and analog hardware and demonstrates effectiveness in CPU implementations by comparison with state-of-the-art heuristics.

What carries the argument

Single-shot feasible-space heuristics that use hardware parallelism to evaluate full feasible neighborhoods in one step and select only moves preserving feasibility.

If this is right

  • The method runs on both CPU and IMC hardware without first mapping the problem to QUBO form.
  • It produces solutions competitive with existing state-of-the-art heuristics when run on ordinary computers.
  • Each iteration can exploit massive parallelism to evaluate every feasible neighbor at once.
  • Feasibility is maintained through choice of moves rather than through extra penalty terms or repair steps.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same single-step neighborhood evaluation could reduce runtime on other permutation-based problems whose feasible moves have similar structure.
  • Actual hardware runs would be needed to confirm whether the claimed single parallel step incurs truly negligible overhead.
  • If the parallelism scales, the approach could handle larger QAP instances than conventional local search allows on CPUs.

Load-bearing premise

The hardware can compute full feasible neighborhoods in a single parallel step with negligible overhead and without introducing new constraint violations.

What would settle it

Executing the heuristic on physical in-memory computing hardware and checking whether iteration time stays constant as neighborhood size grows on standard QAP benchmark instances.

Figures

Figures reproduced from arXiv: 2503.09676 by Arne Heittmann, Chan-Woo Yang, Dmitrii Dobrynin, Dmitri Strukov, Elisabetta Valiante, Giacomo Pedretti, Haesol Im, Ignacio Rozada, John Paul Strachan, Masoud Mohseni, Moslem Noori, Ray Beausoleil, Thomas Van Vaerenbergh.

Figure 2.1
Figure 2.1. Figure 2.1: FIG. 2.1: Relative optimality gaps between objective values observed by three heuristic solvers and optimal [PITH_FULL_IMAGE:figures/full_fig_p005_2_1.png] view at source ↗
Figure 2.2
Figure 2.2. Figure 2.2: FIG. 2.2: Relative optimality gap as a function of the number of iterations for the QAPLIB [27] instances [PITH_FULL_IMAGE:figures/full_fig_p006_2_2.png] view at source ↗
Figure 4.1
Figure 4.1. Figure 4.1: FIG. 4.1: (a) Relationship between two feasible binary solutions 2 [PITH_FULL_IMAGE:figures/full_fig_p012_4_1.png] view at source ↗
Figure 4.2
Figure 4.2. Figure 4.2: FIG. 4.2: The transition of the full-neighbourhood lookup matrices [PITH_FULL_IMAGE:figures/full_fig_p015_4_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: (d), (e), and (f) for an instance of size [PITH_FULL_IMAGE:figures/full_fig_p015_4.png] view at source ↗
Figure 4.3
Figure 4.3. Figure 4.3: FIG. 4.3: Diagram of the computation of the equality (4.17) at variable assignment [PITH_FULL_IMAGE:figures/full_fig_p017_4_3.png] view at source ↗
Figure 5.1
Figure 5.1. Figure 5.1: FIG. 5.1: Objective value trajectories of the [PITH_FULL_IMAGE:figures/full_fig_p023_5_1.png] view at source ↗
Figure 5.2
Figure 5.2. Figure 5.2: FIG. 5.2: Objective value trajectories of the [PITH_FULL_IMAGE:figures/full_fig_p023_5_2.png] view at source ↗
Figure 5
Figure 5. Figure 5: summarizes the number of times the approximate gradient gradient method outperforms the [PITH_FULL_IMAGE:figures/full_fig_p023_5.png] view at source ↗
Figure 5.3
Figure 5.3. Figure 5.3: FIG. 5.3: (a) Range of relative optimality gaps between approximate and exact gradient computations [PITH_FULL_IMAGE:figures/full_fig_p024_5_3.png] view at source ↗
Figure 5.4
Figure 5.4. Figure 5.4: FIG. 5.4: Proportion of 100 trials in which the approximate or exact gradient method reaches the optimal [PITH_FULL_IMAGE:figures/full_fig_p024_5_4.png] view at source ↗
Figure 5.5
Figure 5.5. Figure 5.5: FIG. 5.5: Ratio of the average runtime using the exact gradient method versus the approximate gradient [PITH_FULL_IMAGE:figures/full_fig_p024_5_5.png] view at source ↗
Figure 5
Figure 5. Figure 5: shows rel [PITH_FULL_IMAGE:figures/full_fig_p025_5.png] view at source ↗
Figure 5.6
Figure 5.6. Figure 5.6: shows rel error over the first 1000 iterations for instances formulated by Skorin–Kapov (“sko”), Li and Pardalos (“lipa”), and Taillard (“tai”). We observe a consistent trend across all three classes, indicating that the contribution of Ei relative to ∆i diminishes as the problem size increases, hence, the impact of omitting the error terms becomes negligible in large-scale instances. 0 500 1000 Iteratio… view at source ↗
Figure 5.7
Figure 5.7. Figure 5.7: FIG. 5.7: Computation load distribution on six QAPLIB instances. The runtimes over 10 [PITH_FULL_IMAGE:figures/full_fig_p026_5_7.png] view at source ↗
read the original abstract

Research into the development of special-purpose computing architectures designed to solve quadratic unconstrained binary optimization (QUBO) problems has flourished in recent years. It has been demonstrated in the literature that such special-purpose solvers can outperform traditional complementary metal--oxide--semiconductor architectures by orders of magnitude with respect to timing metrics on synthetic problems. However, they face challenges with constrained problems such as the quadratic assignment problem (QAP), where mapping to binary formulations such as QUBO introduces overhead and limits parallelism. In-memory computing (IMC) devices, such as memristor-based analog Ising machines, offer significant speed-ups and efficiency gains over traditional CPU-based solvers, particularly for solving combinatorial optimization problems. In this work, we present a novel hardware-aware QAP optimization framework designed for IMC hardware. By co-designing the local search heuristic with the underlying hardware, we exploit the intrinsic massive parallelism that allows for computing of full neighbourhoods simultaneously to make update decisions. We ensure binary solutions remain feasible by selecting local moves that lead to neighbouring feasible solutions, leveraging feasible-space search heuristics and the underlying structure of a given problem. Our approach is compatible with both digital computers and analog hardware. We demonstrate its effectiveness in CPU implementations by comparing it with state-of-the-art heuristics for solving the QAP.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper proposes a hardware-aware local-search framework for the Quadratic Assignment Problem that co-designs a feasible-space heuristic with in-memory computing (IMC) architectures. By evaluating full neighborhoods in one parallel step and restricting updates to feasible neighboring solutions, the method aims to avoid QUBO-mapping overhead while remaining compatible with both digital CPUs and analog memristor-based Ising machines; effectiveness is shown via CPU implementations benchmarked against existing QAP heuristics.

Significance. A validated single-shot feasible-space heuristic on IMC hardware would remove a key barrier to applying analog solvers to constrained combinatorial problems and could deliver substantial speed and energy gains over CPU baselines. The CPU results supply a necessary first benchmark, but the absence of any hardware mapping or timing measurements means the central hardware-compatibility claim remains untested.

major comments (2)
  1. [Abstract] Abstract: the assertion that the heuristic 'allows for computing of full neighbourhoods simultaneously' on IMC hardware is unsupported; the manuscript reports only CPU implementations and provides neither a hardware mapping, crossbar simulation, nor any analog timing/energy data that would confirm single-step parallel evaluation of feasible neighborhoods.
  2. [Abstract] Abstract: the claim that binary solutions 'remain feasible by selecting local moves that lead to neighbouring feasible solutions' is presented as hardware-compatible, yet no mechanism is described for realizing the feasible-move filter in analog IMC circuitry without extra digital correction logic or risk of introducing uncorrectable constraint violations.
minor comments (1)
  1. The abstract refers to comparisons with 'state-of-the-art heuristics' but does not name the specific algorithms or report quantitative metrics (runtime, solution quality) in the provided text.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed review and for identifying points where the abstract could be read as overstating hardware results. The manuscript presents an algorithmic co-design whose CPU implementation is fully benchmarked; the hardware-compatibility claims rest on the design choices that map directly onto IMC parallelism and feasible-space moves. We will revise the abstract and add clarifying text to ensure no unsupported performance assertions appear. No hardware experiments or crossbar simulations were performed, so we limit claims to algorithmic compatibility.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the assertion that the heuristic 'allows for computing of full neighbourhoods simultaneously' on IMC hardware is unsupported; the manuscript reports only CPU implementations and provides neither a hardware mapping, crossbar simulation, nor any analog timing/energy data that would confirm single-step parallel evaluation of feasible neighborhoods.

    Authors: We agree the phrasing in the abstract can be misread as claiming executed single-shot evaluation on IMC hardware. The heuristic is constructed so that a single parallel read-out of the entire neighborhood is sufficient to select the next feasible move; this property is a direct consequence of the feasible-space formulation and matches the native parallelism of IMC crossbars. The CPU implementation evaluates the same neighborhood structure sequentially to obtain the reported benchmarks. We will revise the abstract to read that the heuristic is designed to exploit single-shot neighborhood evaluation on IMC hardware, while making explicit that all reported results are from CPU runs and that hardware validation remains future work. revision: yes

  2. Referee: [Abstract] Abstract: the claim that binary solutions 'remain feasible by selecting local moves that lead to neighbouring feasible solutions' is presented as hardware-compatible, yet no mechanism is described for realizing the feasible-move filter in analog IMC circuitry without extra digital correction logic or risk of introducing uncorrectable constraint violations.

    Authors: The feasible-space restriction is enforced at the algorithmic level by enumerating only the moves that preserve the permutation structure of QAP solutions; this enumeration can be performed either in digital pre-processing or by a lightweight digital controller that gates the analog update. The manuscript does not claim an all-analog realization of the filter. We will add a short paragraph in the methods section describing this hybrid interface and will tone down the abstract to state that the approach remains compatible with IMC hardware when a feasible-move selector (digital or hybrid) is present. revision: yes

Circularity Check

0 steps flagged

No circularity: heuristic description contains no derivations, fits, or self-referential reductions

full rationale

The manuscript describes an algorithmic framework for feasible-space local search co-designed for IMC hardware. No equations, parameters, or first-principles derivations appear in the provided text. The central claims rest on stated design choices and CPU-based empirical comparisons rather than any quantity derived from itself by construction. No self-citations, ansatzes, or uniqueness theorems are invoked in a load-bearing way. The derivation chain is therefore self-contained and does not reduce to its inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review supplies no explicit free parameters, axioms, or invented entities; the central claim implicitly assumes standard definitions of QAP and local search plus an unverified hardware parallelism property.

pith-pipeline@v0.9.0 · 5817 in / 1091 out tokens · 25940 ms · 2026-05-22T23:47:26.252240+00:00 · methodology

discussion (0)

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Reference graph

Works this paper leans on

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