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REVIEW 3 major objections 7 minor 30 references

EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks

T0 review · 3 major / 7 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read The paper claims that Apple's exclusive System-Level Cache can be coerced into an occupancy side-channel that lets an attacker on one CPU cluster observe GPU and remote-cluster activity, enabling website fingerprinting, cross-origin pixel…

desk verdict Solid empirical first cut at an exclusive-SLC occupancy channel on Apple M-series, but the validation doesn't fully rule out DRAM contention as the real carrier. read the letter →

arxiv 2504.13385 v1 pith:CAIZCR2Z submitted 2025-04-18 cs.CR cs.AR

Tianhong Xu , Aidong Adam Ding , Yunsi Fei This is my paper · ORCID
classification cs.CRcs.AR
keywords cacheoccupancyattackSystem-LevelAppleM-seriesSoCsGPUsidechannelwebsitefingerprintingpixelstealingscreencapturingexclusive
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that Apple's System-Level Cache, despite being exclusive to CPU caches, can be turned into a usable occupancy side-channel: an attacker's JavaScript or native process on one CPU cluster can infer what the GPU and other CPU clusters are doing by timing evictions from the shared SLC. The authors reverse-engineer the M1 SLC (128-byte lines, hybrid inclusive/exclusive policy, set-index bits above bit 13, pseudo-random replacement) and design an access pattern that fills the SLC while bypassing L2. If the channel works as claimed, a background web page can identify which website the user visits, steal individual pixels from a cross-origin iframe, and even recover on-screen digits or barcodes at 57-row granularity. This matters because it expands cache-occupancy attacks out of the same-core, same-cluster setting into cross-cluster and CPU-GPU settings on Apple's heterogeneous chips.

What carries the argument

The central object is the SLC occupancy channel, a prime-reload-style profiling loop in which the spy repeatedly steps through a buffer that fills the SLC but bypasses the L2. It is made to work by two mechanisms: the alternated-order access pattern (each profiling round runs the buffer in the opposite direction, stopping LRU self-eviction) and the stride-8192 data structure (contiguous virtual addresses with fixed low 13 bits, so the L2 sees only a small set of its index bits while the SLC, which indexes from bit 14 upward, sees the whole buffer). For the screen attack, a dual-set prime-and-reload with two staggered primes produces a short observation window; differences in evicted-line counts between the two reloads isolate GPU memory activity within a roughly 0.4 ms slice of a 16.7 ms frame.

What would settle it

Run the paper's slide experiment—alternating solid black and solid white full-screen frames while measuring evicted SLC lines during rendering—on the same M1 machine before and after a macOS or GPU-driver update; if GPU memory usage no longer tracks the zero-pixel count, the screen-capturing and pixel-stealing attacks fail on that platform.

Watch

Extended reading notes

Core claim

On Apple M-series chips the System-Level Cache is not a smaller mirror of the CPU caches: it is exclusive with respect to the CPU's L1/L2 and inclusive with respect to the GPU's cache. That exclusiveness means an ordinary occupancy buffer never fills the SLC, because warm data stays in L2. The paper's discovery is a way around this: by exploiting the different set-indexing of L2 and SLC, a buffer accessed with 8 KB stride occupies the SLC while using only about 1/64 of L2, and by alternating the traversal direction between profiling rounds the spy avoids self-eviction artifacts. The resulting SLC occupancy channel tracks victim memory traffic linearly, in intra-cluster, inter-cluster, and CPU-GPU settings, and it is sensitive enough to detect GPU memory-usage differences tied to the number of zero-valued pixels in a rendered frame. From that sensitivity the paper builds website fingerprinting, pixel stealing, and screen-capturing attacks, plus a stride-based SLC masking countermeasure.

Load-bearing premise

The screen and pixel attacks rest on the undocumented empirical link between how many zero-valued pixels a frame has and how much GPU memory it uses; if a macOS update, GPU driver, or newer M-series chip changes or removes that link, those attacks lose their signal.

Editorial extensions

If this is right

  • Website fingerprinting: an attacker can identify which of 100 top websites a user visits with roughly 87–92% accuracy even when spy and victim browsers are assigned to different CPU clusters, where the prior L2 occupancy channel drops to about 33–38%.
  • Pixel stealing: an attacker can distinguish black from white pixels in a cross-origin iframe with 84–94% accuracy at about 2 seconds per pixel in Chrome, and the attack works despite constant-time SVG filter implementations and the CVE-2023-38599 fix.
  • Screen capturing: the channel can recover ITF barcode digits with about 90% accuracy when narrow bars are at least 20 pixels tall, and single Arabic digits with about 91% accuracy, using 57-row vertical granularity on a 1600-row screen.
  • The countermeasure: a stride-based SLC masking buffer of at least 12 MB suppresses the SLC occupancy channel, with under 5% single-core and under 10% multi-core performance overhead in the paper's Geekbench measurements.
  • The SLC channel works in intra-cluster, inter-cluster, and CPU-GPU scenarios, whereas the prior L2 occupancy channel only works in the intra-cluster setting.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • I infer (beyond the paper): the same stride-based SLC-filling trick should transfer to other heterogeneous SoCs whose last-level cache is exclusive and whose set-indexing can be discovered, so the threat is not unique to Apple.
  • I infer: the zero-pixel-to-GPU-memory correlation is strong evidence of hardware frame-buffer compression; the paper leaves the exact mechanism undocumented, but if compression is what drives the signal, the channel might also distinguish large solid-color regions by color channel rather than only by zero count.
  • I infer: the paper's SLC masking and L2 masking are complementary rather than alternatives; an OS-level defense would likely need both, and their performance costs would combine.
  • I infer: the screen-capturing attack's practical reach is bounded by its own stated conditions—still displays, mostly solid-color content, and roughly five-minute capture—so the realistic near-term targets are codes, passwords, and verification digits, not general pixel-level screen content.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. The paper reverse-engineers the System-Level Cache (SLC) of Apple M-series SoCs and proposes an SLC-specific cache occupancy side channel. On an M1, the authors measure SLC hit latency, infer that the SLC is exclusive with respect to CPU caches and inclusive with respect to the GPU cache, map the set-index bits (excluding the low 13 bits), and observe pseudo-random replacement. To fill the SLC while bypassing the L2, they introduce an alternated-order access pattern and an 8-KB strided buffer. They evaluate the resulting channel against L2 and total-occupancy channels in intra-cluster, inter-cluster, and CPU-GPU scenarios. They then build three attacks: a closed-world website fingerprinting attack over 100 Alexa sites (87-92% accuracy in cross-cluster scenarios, compared with 33-38% for the prior L2 channel), a cross-origin pixel-stealing attack that distinguishes black and white pixels via GPU memory usage (92-94% on Chrome, 84-85% on Safari), and a screen-snooping attack that resolves 28 vertical screen bands (57 rows each) and applies them to ITF barcodes and printed digits. Finally, they propose cache-masking countermeasures with reported performance overheads below 10% in multi-core benchmarks.

Significance. If the central mechanism is correct, this is a significant contribution: it is the first occupancy side channel that specifically targets the exclusive SLC of Apple Silicon, and it extends occupancy attacks to inter-cluster and CPU-GPU scenarios that prior L2-based channels cannot reach. The paper has real strengths: attacks are evaluated on three SoCs and multiple browsers; the website fingerprinting uses a 100-site closed-world dataset with clean-environment controls; the pixel and screen attacks are demonstrated end-to-end; and the methodology is described in enough detail to reproduce the reverse engineering. The paper also appropriately compares against the previous L2 channel. However, the headline claims rest on two points that need strengthening: the SLC-occupancy interpretation of the measured signal is not separated from DRAM/memory-controller contention, and the screen-capturing attack is substantially more constrained than the abstract's "retrieve any screen display" language. With additional control experiments and more careful claims, the result would be a valuable advance for the cache-occupancy and heterogeneous-SoC security literature.

major comments (3)
  1. [Section 3.5, Figure 5] The validation of the SLC occupancy channel does not separate SLC occupancy from DRAM/memory-controller contention. The dependent variable is the spy's total profiling time while the victim buffer size grows; both the inter-cluster victim (e-core loads) and the GPU victim generate DRAM traffic that grows with buffer size, and the spy's strided buffer also misses to DRAM. A memory-bandwidth or memory-controller contention channel would yield the same monotone profiles even if the victim never allocated lines in the SLC. The paper needs controls, for example a victim workload that keeps DRAM traffic constant while varying SLC allocation, and a workload that varies DRAM traffic while holding SLC allocation fixed. Without these, the central claim of an exclusive-SLC occupancy channel (abstract and Section 3.5) is not yet established.
  2. [Section 6.1, Figure 9] The pixel-stealing and screen-capturing attacks depend on the empirical premise that GPU memory usage falls as zero-valued pixels increase, attributed without public documentation to GPU compression. The paper itself acknowledges in Section 6.1 that it is challenging to pinpoint the exact reason for this correlation. If the correlation is instead a consequence of DRAM traffic volume (for example, compressed data transfers fewer bytes), the attacks would still be interesting but would not validate the claimed SLC occupancy mechanism. A concrete test would be to render frames with identical GPU memory footprints but different data compressibility, and to check whether the SLC-hit-based metric, rather than total access time, tracks the difference.
  3. [Abstract, Sections 6.2-6.3] The abstract and introduction overstate the screen-capturing attack. The abstract says the adversary can "retrieve any screen display," but Section 6.2 reports that the technique works only when more than 90% of the screen consists of large solid-color blocks (each exceeding 256 by 256 pixels), requires a completely still screen, and takes about five minutes per measurement. Section 6.3.2 and Table 5 further show Top-1 accuracy of 52.9% for two digits and 21.4% for three digits, with no ability to determine digit order. These constraints should be stated in the abstract and introduction, and the "any screen display" claim should be qualified to solid-color-dominated static screens under restrictive conditions.
minor comments (7)
  1. [Section 3.5] The reported buffer sizes of 120,000 L2 lines, 300,000 SLC-saturation lines, and 80,000 SLC-buffer lines are not reconciled with the stated 8 MB SLC and 12 MB L2 capacities; with 128-byte lines these correspond to 15.36 MB, 38.4 MB, and 10.24 MB, respectively. Please clarify whether these are nominal capacities or include the effects of random replacement and prefetching.
  2. [Section 3.2] The 160-tick and 300-tick thresholds are calibrated on one M1 device; the paper does not report whether these thresholds were recalibrated on the M1 Pro and M3 Pro before applying the channel in Sections 4 and 5, so please state the calibration procedure per device.
  3. [Table 2] The website fingerprinting accuracies are reported as single numbers without confidence intervals or error bars; given the 90-10 cross-validation split, please report the variance across folds or repeated runs.
  4. [Table 3] For the pixel recognition accuracies, please state the number of pixels tested and whether accuracy is per-pixel across a single page or across repeated trials, since this affects the statistical strength of the 92-94% claims.
  5. [Section 6.1, Figure 9d] The text describes pink as RGB (0,255,255), which is cyan; please correct the color naming in the figure caption or the text.
  6. [Section 6.2, Figure 11] The single-frame trace with 28 epochs is presented without variability information; please include repeated-frame statistics or a representative confidence band to support the claimed stability of the flash-point pattern.
  7. [Section 7.1, Figure 16] Please clarify whether the 12 MB SLC masking scheme uses a single buffer or the new-buffer-per-iteration enhancement, since Figure 16a explicitly distinguishes the two cases for the L2 masking scheme.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the attacks are empirically validated against external benchmarks rather than derived from fitted parameters or self-citations.

full rationale

The paper's central claims are empirical demonstrations of side-channel attacks, not claims derived from fitted parameters or self-referential inputs. The SLC occupancy channel is characterized through independent reverse-engineering experiments (latency thresholds, set-index mapping, replacement policy) whose results are then used to build the channel; the attack validations then test that channel against fresh measurements. The website fingerprinting attack collects traces from the Alexa Top 100 websites and evaluates with SVM using 90-10 cross-validation, so accuracy is measured on held-out traces rather than on the training data. The pixel-stealing attack first measures the SLC access-time distributions for black versus white pixels and then applies a threshold to new pixels; this is standard supervised evaluation, not a fitted input renamed as a prediction. The screen-capturing attack builds a pattern library from an independently measured relationship between the fraction of zero-valued pixels and GPU memory usage, then matches fresh flash-point traces against that library; the mapping is not fitted to the attack outcome. No load-bearing self-citation appears, and no uniqueness theorem or ansatz is imported from the authors' prior work. The skeptic's concern that the inter-cluster and CPU-GPU signals might reflect DRAM or memory-controller contention rather than SLC occupancy is a correctness or validity risk, not a circularity, and the paper's own experiments do not reduce its claimed outputs to its inputs by construction. The derivation chain is therefore self-contained with respect to circularity.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

All load-bearing assumptions come from the authors' own reverse engineering or from empirical correlations that Apple does not document. There are no invented physical entities. The free parameters are experimental thresholds and buffer sizes tuned to the target device, which are typical for cache side-channel papers but should be treated as tuned, not derived.

free parameters (4)
  • SLC/L2 timing thresholds = 160 ticks and 300 ticks
    Chosen in Section 3.2 to classify L1/L2 hits, SLC hits, and SLC misses; the channel depends on these boundaries.
  • Pixel discrimination threshold = Not reported
    Selected in Section 5.2 to achieve 92% accuracy on M1; the reported accuracy depends on this post hoc choice.
  • Occupancy buffer sizes = 80,000 (SLC), 120,000 (L2), 300,000 (total) cache lines
    Tuned to the measured L2 and SLC capacities in Section 3.5; the SLC channel uses 80,000 cache lines.
  • Screen observation window = 0.4 ms window, 0.04 ms increment
    Chosen in Section 6.2 to capture frame flash points without overlapping the prime and reload operations.
assumptions (5)
  • domain assumption The SLC is exclusive to CPU caches and inclusive to the GPU cache.
    Reverse-engineered by the authors (Section 3.4, Appendix A.1) but not publicly documented; the entire channel design rests on it.
  • domain assumption GPU memory usage decreases as the number of zero-valued pixels increases.
    Empirical hypothesis in Section 6.1; the pixel stealing and screen capture attacks depend on this correlation, whose mechanism is not documented by Apple.
  • domain assumption The SLC replacement policy is pseudo-random and independent of access order.
    Inferred from experiments in Appendix A.3; used to explain why the SLC utilization reaches only about 90%.
  • domain assumption The SLC set index excludes the lowest 13 address bits and uses bits 14 and above.
    Reverse-engineered in Appendix A.2; this is the basis for the stride-8192 buffer that fills the SLC while bypassing the L2 cache.
  • domain assumption The macOS scheduler places background Safari on efficiency cores while other browsers stay on performance cores.
    Inferred in Section 4.2 from the observed success and failure of the L2 channel; used to construct the inter-cluster scenario.

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Cite this review

Pith. "Pith review of EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks." pith.science (2026). https://pith.science/paper/CAIZCR2Z

@misc{pith2026250413385,
  author       = {Pith},
  title        = {Pith review of: EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CAIZCR2Z}},
  note         = {Machine review of arXiv:2504.13385}
}
read the original abstract

Cache occupancy attacks exploit the shared nature of cache hierarchies to infer a victim's activities by monitoring overall cache usage, unlike access-driven cache attacks that focus on specific cache lines or sets. There exists some prior work that target the last-level cache (LLC) of Intel processors, which is inclusive of higher-level caches, and L2 caches of ARM systems. In this paper, we target the System-Level Cache (SLC) of Apple M-series SoCs, which is exclusive to higher-level CPU caches. We address the challenges of the exclusiveness and propose a suite of SLC-cache occupancy attacks, the first of its kind, where an adversary can monitor GPU and other CPU cluster activities from their own CPU cluster. We first discover the structure of SLC in Apple M1 SOC and various policies pertaining to access and sharing through reverse engineering. We propose two attacks against websites. One is a coarse-grained fingerprinting attack, recognizing which website is accessed based on their different GPU memory access patterns monitored through the SLC occupancy channel. The other attack is a fine-grained pixel stealing attack, which precisely monitors the GPU memory usage for rendering different pixels, through the SLC occupancy channel. Third, we introduce a novel screen capturing attack which works beyond webpages, with the monitoring granularity of 57 rows of pixels (there are 1600 rows for the screen). This significantly expands the attack surface, allowing the adversary to retrieve any screen display, posing a substantial new threat to system security. Our findings reveal critical vulnerabilities in Apple's M-series SoCs and emphasize the urgent need for effective countermeasures against cache occupancy attacks in heterogeneous computing environments.

Figures

Figures reproduced from arXiv: 2504.13385 by the authors.

Figure 1
Figure 1. Cache structure of Apple M1 The Apple M-series SoCs, based on ARM’s big.LITTLE architec￾ture, herald a significant shift towards efficiency and performance in Mac computers [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Hit time of different cache levels To establish a reli￾able SLC occupancy side-channel, we first need to recognize whether a piece of data is present in the SLC (i.e., an SLC cache hit) by measuring data ac￾cess latencies. Prior works [8, 18] have quantified L1 hit, L2 hit, and L2 miss times for the Apple M1. However, they have not differenti￾ated between SLC hits and SLC misses, both of which are catego￾rized as L2… view at source ↗
Figure 3
Figure 3. L2 & SLC hits under different access patterns [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (14 more)
Figure 4
Figure 4. Figure 4: Cache filling with different data structure [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Spy access time vs. victim activities [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 8
Figure 8. Figure 8: Pixel stealing attack The security implications of such attacks are significant. Many popular websites are allowed to be embedded via iframes on a third￾party website while displaying user identity information some￾where on the page, for example, Wikipedia and LinkedIn…
Figure 9
Figure 9. Figure 9: Evicted cache lines for different slides [PITH_FULL_IMAGE:figures/full_fig_p009_9.png]
Figure 13
Figure 13. Figure 13: Screen display snooping attack method (a) Characters (b) Flash epoch segments [PITH_FULL_IMAGE:figures/full_fig_p010_13.png]
Figure 12
Figure 12. Figure 12: Correlation between a trace of flash points and [PITH_FULL_IMAGE:figures/full_fig_p010_12.png]
Figure 15
Figure 15. Figure 15: Attack accuracy vs. the narrower bar width [PITH_FULL_IMAGE:figures/full_fig_p011_15.png]
Figure 13
Figure 13. Figure 13: Such digits may con￾tain sensitive information, such as verification codes and passwords, that the attacker aims to steal. Ini￾tially focusing on a single digit, the results of this attack are presented in a confusion matrix, reveal￾ing an accuracy rate of 91%. Most d…
Figure 16
Figure 16. Figure 16: Effectiveness of the proposed countermeasures [PITH_FULL_IMAGE:figures/full_fig_p012_16.png]
Figure 17
Figure 17. Figure 17: Performance impact of mitigations 8 Conclusion In this paper, we presented a comprehensive study of cache occu￾pancy attacks targeting the System-Level Cache (SLC) in Apple M-series SoCs, revealing critical vulnerabilities in these modern het￾erogeneous computing syst…
Figure 20
Figure 20. Figure 20: Cache utilization with different strides [PITH_FULL_IMAGE:figures/full_fig_p014_20.png]
Figure 18
Figure 18. Figure 18: SLC capacities [PITH_FULL_IMAGE:figures/full_fig_p014_18.png]
Figure 3
Figure 3. Figure 3: However, our experimental results, shown in Figure 19, [PITH_FULL_IMAGE:figures/full_fig_p014_3.png]
Figure 21
Figure 21. Figure 21: b, the SLC utilization only reaches about 90%. (a) L2 hits (b) SLC hits [PITH_FULL_IMAGE:figures/full_fig_p015_21.png]

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