Surface-code Superconducting Quantum Processors: From Calibration To Logical Performance

Hany Ali

REVIEW 1 major objections 4 minor 1 cited by

Surface-code Superconducting Quantum Processors: From Calibration To Logical Performance

T0 review · 1 major / 4 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read Run under repeated error detection, a seven-transmon distance-2 surface code can initialize, measure, and gate a logical qubit through a universal single-qubit set, with fault-tolerant variants outperforming non-fault-tolerant ones.

desk verdict Solid thesis compilation with two strong published experiments and useful engineering content, but the supplementary claim that all logical error rates beat the best physical error rates is contradicted by the paper's own numbers. read the letter →

arxiv 2504.17082 v1 pith:LMIYBDIQ submitted 2025-04-23 quant-ph

Hany Ali This is my paper · ORCID

classification quant-ph

keywords surfacecodequantumerrordetectionlogicalqubitsuperconductingtransmonfault-tolerantoperationsPaulitransfermatrixleakagereductionsoft-informationdecoding

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This thesis argues that the surface-code architecture can be carried through the entire experimental stack on flux-tunable superconducting transmons, from calibrated two-qubit gates to logical-level operations. Its central experimental claim is that a distance-2 surface code using seven transmons supports a complete logical-qubit operation set—initialization anywhere on the logical Bloch sphere, measurement in all three cardinal bases, and universal single-qubit logical gates—while repeated stabilizer measurements detect errors and post-selection discards runs in which an error is seen. For every operation type, the fault-tolerant implementation outperforms the non-fault-tolerant one (logical readout fidelities of 99.8% for $Z_L$, 98.7% for $X_L$, 91.4% for $Y_L$), and the logical error rate per error-detection round is below the best physical-qubit error rate. Around this result the thesis develops the supporting building blocks: a sudden net-zero controlled-Z gate reaching 99.93% fidelity, automated calibration of a 17-transmon surface code, leakage-reduction units, and soft-information decoding. If the central claim holds, small surface codes can function as testbeds for fault-tolerant protocols rather than as merely stabilized memories.

What carries the argument

The load-bearing object is the distance-2 surface-code logical qubit: seven flux-tunable transmons, four data and three ancilla, arranged so that the codespace is the even-parity subspace of the stabilizer set $S = \{Z_{D1}Z_{D3},\; X_{D1}X_{D2}X_{D3}X_{D4},\; Z_{D2}Z_{D4}\}$. The stabilizer measurements project the data into the codespace and flag errors by returning $-1$; because this code cannot uniquely identify every error, the protocol post-selects runs with no detected error. Fault tolerance is achieved by designing each logical operation so that any single fault either yields a non-trivial syndrome or leaves the desired logical state with a detectable error; the order of CZ gates in the weight-4 stabilizer circuit is what prevents ancilla faults from becoming logical errors. The second carrying mechanism is the logical Pauli transfer matrix, a $4\times 4$ real matrix mapping input logical Pauli expectation values to outputs, which lets logical gates be benchmarked with a single average fidelity. The third is the sudden net-zero (SNZ) controlled-Z pulse, whose two square half-pulses realize an exact Mach-Zehnder interferometer for the $|11\rangle$-$|02\rangle$ transition, giving 99.93% gate fidelity and a regular leakage landscape that makes tuneup simple.

What would settle it

Run the logical $X_L$ measurement with a deliberately inserted single-qubit pre-rotation error (for example, a 1% under-rotation on one data qubit) while keeping data-qubit readout unchanged, and extract $F_R^L$ with the paper's assignment-probability-matrix method; if the extracted value moves materially away from 98.7%, the negligible-single-qubit-error premise is false and the quoted logical readout fidelities need recalibration.

Watch

Extended reading notes

Core claim

The core discovery is that a distance-2 surface code (Surface-7), four data transmons and three ancillas, can be operated as a logical qubit under repeated error detection, not just as a stabilized quantum memory. The work demonstrates initialization of arbitrary logical states, fault-tolerant logical measurement in the $Z_L$ and $X_L$ bases, a non-fault-tolerant $Y_L$ measurement, and a universal single-qubit logical gate set that includes transversal $R_X^{\pi}$ and $R_Z^{\pi}$ gates and gate-by-measurement $R_X^{\pi/2}$ and $T_L$ gates. It characterizes the gates with a logical Pauli transfer matrix, reporting average logical gate fidelities of 97.9%, 98.1%, 95.6%, and 97.3% for those four gates. For each operation type the fault-tolerant variant beats the non-fault-tolerant variant, and logical error rates per round (0.15% to 0.67%) lie below the best physical-qubit $T_1$ and $T_2$ error rates. The work further compares two scalable stabilizer-measurement schemes, pipelined and parallel, finding the pipelined scheme slightly better, and identifies leakage to higher transmon states during CZ gates as the dominant error source not captured by standard decoherence and readout models.

Load-bearing premise

The quoted logical readout fidelities rest on the assumption that single-qubit gate errors during the measurement pre-rotations are negligible compared with data-qubit readout errors; if that premise fails, the fault-tolerant versus non-fault-tolerant readout comparison shifts.

Editorial extensions

If this is right

A complete logical operation set, including a non-Clifford $T_L$ gate, can be executed on a distance-2 code with repeated error detection, providing a template for the logical-level primitives needed in higher-distance surface codes.
Fault-tolerant circuit design pays off even at the smallest code distance: every operation type shows a measurable improvement of the fault-tolerant variant over the non-fault-tolerant variant.
Logical error rates per round below the best physical qubit error rates imply that error detection already confers a logical benefit, and that the path to fault tolerance is through code distance rather than through better physical qubits alone.
A scalable stabilizer-measurement scheme with distance-independent cycle time, such as the pipelined scheme, can be used without sacrificing logical performance; its per-cycle error rate is about 3% lower than the parallel scheme.
Leakage out of the computational subspace, chiefly from CZ gates, must be actively managed in repeated stabilizer experiments; post-selection and leakage-reduction units are the near-term tools, and the thesis shows both working.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the negligible-single-qubit-error premise in the logical-readout analysis is relaxed, the exact quoted $F_R^L$ values (99.8/98.7/91.4%) would need recomputation; the fault-tolerant ordering might survive, but the margins could narrow.
The same assignment-probability-matrix method used to extract logical readout fidelity without initialization corruption could be applied directly to the distance-3 code, giving a readout benchmark that is independent of state-preparation errors.
A natural next experiment is to run the Chapter 3 protocol on a distance-3 device with the automated calibration, leakage reduction, and soft-information decoding of Chapters 4, 5, and 7; if the per-round logical error rate drops when distance increases, the exponential-suppression claim would be tested directly.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short version: this is a competent experimental thesis built on two strong published results, and the engineering chapters are worth reading. But the supplementary claim that every logical error rate is below the best physical error rate does not survive the paper's own numbers. For the pipelined 840 ns cycle, the j+_L logical error rate is 0.49% while the best T2 dephasing error is about 0.36%; so the "all states" sentence in Supp. 3.6.5 is wrong. That is a real flaw, but it is a comparison claim in the supplement, not one of the load-bearing experimental results.

What is genuinely new: the SNZ CZ gate and the Surface-7 logical operations were published in PRL and Nature Physics, and they are strong experiments with standard benchmarking, error bars, and linked processed data. The thesis adds useful unpublished material: Graph-Based Tuneup for a 17-transmon device, engineering around TLS defects and frequency trimming, leakage-reduction units, and soft-information decoding for a distance-3 bit-flip code. I could not fully check Chapters 4 and 6 because the text was truncated and no data/code are linked for those chapters; the engineering content looks plausible and is clearly presented.

Soft spots, in order of importance. First, the leakage per CZ gate L1 in the Chapter 3 simulation is explicitly a fit parameter, and the authors admit their histogram-based estimates are not accurate enough to pin it down. That weakens the quantitative statement about leakage being the dominant missing error source. A direct leakage measurement, even on one gate, would firm this up. Second, the stress-test issue above: the logical-vs-physical comparison should be corrected or removed. Third, the logical readout fidelities rely on the assumption that single-qubit gate errors are negligible compared to readout errors; that is probably safe given Table 5.1, but it is an assumption and should be stated as such. The self-citation pattern is not a problem here; the earlier papers are independent benchmarks, and this is a thesis.

Who should read it: experimentalists working on small surface codes and calibration automation, and theorists who want concrete numbers for error models. It deserves peer review if submitted as a review or monograph; a referee should ask for the leakage free parameter to be addressed and the unsupported comparison fixed. It is not a desk reject.

Referee Report

1 major / 4 minor

Summary. This PhD thesis compiles experimental work on flux-tunable transmon surface-code processors. Chapter 2 presents the SNZ controlled-Z gate, reporting up to 99.93% gate fidelity and 0.10% leakage. Chapter 3 demonstrates a distance-2 Surface-7 logical qubit stabilized by repeated error detection, including logical initialization to arbitrary states, logical measurement in the ZL/XL/YL bases, and a universal single-qubit logical gate set; a central claim is that fault-tolerant variants outperform non-fault-tolerant variants. Chapter 4 describes automatic calibration and benchmarking of a 17-transmon Surface-17 device, including techniques for coping with two-level-system defects and frequency-targeting errors. Chapters 5-7 cover leakage reduction units, calibration of QEC cycles, and soft-information decoding for a bit-flip code. The central narrative is that small-scale surface-code error detection can realize a complete logical-qubit operation set and that the building blocks can be calibrated and optimized for larger codes.

Significance. If the results hold, the thesis provides valuable experimental milestones for surface-code quantum error correction with superconducting qubits: a complete logical-operation suite on a distance-2 surface code, a high-fidelity and easily tuned two-qubit gate, automatic calibration at the 17-qubit scale, and a demonstrated benefit of soft-information decoding. Strengths include the availability of processed data for Chapters 2 and 3, the use of standard randomized benchmarking and tomography with quoted error bars, the detailed comparison of pipelined versus parallel stabilizer readout, and the transparent treatment of leakage as a free parameter in simulations. The SNZ gate argument is concise and analytical in its ideal limit. However, one supporting comparison in the Chapter 3 supplementary material is internally inconsistent and needs correction before the manuscript can be accepted as a coherent record of logical performance.

major comments (1)

[Supplement 3.6.5, Eq. (3.23), Fig. 3.9] The statement that "the logical error rates for all states ... are lower than the corresponding best physical error rates" is not supported by the paper's own numbers. For the |+_L> state, the fitted per-cycle logical error rate is 0.49%, while Eq. (3.23) with the best measured echo T2 = 117 us (D4, Table 3.2) and the 840 ns pipelined cycle gives a physical dephasing error of 1 - exp(-840 ns / (2 x 117 us)) ~ 0.36%; the logical rate is therefore about 36% larger, contradicting the "all states" claim. In addition, the comparison for |0_L> uses the T1 error of the physical |1> state (Eq. 3.22), which is not the corresponding error for a physical qubit prepared in |0>; a state-matched comparison would make the |0_L> rate of 0.43% per cycle look worse, not better. Please correct or remove this comparison, or present a state-matched and cycle-matched physical baseline.

minor comments (4)

[Section 3.6.11 and Section 3.2.1] The cross-reference to "Table 5.1" in these sections should point to Table 3.2, the device-characteristics table in Chapter 3; the current numbering is confusing because Chapter 5 has its own tables.
[Section 3.4] The text contains an unresolved citation "[77, 128?]" with a literal question mark; this reference should be completed or removed.
[Eq. (3.23)] The notation 1 - e^{-t/T2/2} is ambiguous; please write the intended expression explicitly, e.g., 1 - exp(-t/(2T2)) or 1 - exp(-2t/T2), and ensure it matches the physical dephasing model used in the comparison.
[Chapter 4, title and figure captions] There are several typographical errors, including "benchmakring" in the Chapter 4 title and headings, "envolved" in Section 3.4, and "uncertasinties" in the Fig. 4.3 caption; these should be corrected in a final proofreading pass.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: central claims are grounded in external benchmarks and measured data, not self-referential reductions.

full rationale

The central derivations are self-contained against external benchmarks. Chapter 3's logical fidelities are obtained from tomographic reconstruction using ideal Pauli operators and maximum-likelihood estimation, with readout errors corrected via an experimentally measured 16x16 assignment matrix; the resulting logical readout fidelities are corrected estimates, not fitted predictions. The error-detection rates are extracted by exponential fits to post-selected fractions, and the logical error rates by fits to measured expectation-value decay; these are standard parameter extractions, not circular predictions. The simulation in Supplement 3.6.14 treats the leakage per CZ gate L1 as an explicit free parameter to match simulation to experiment, explicitly disclaiming accuracy; this is honest model fitting, not a fitted input renamed as a prediction. Self-citations to Refs. [69], [74], and [98] supply hardware-architecture and gate-implementation context; none is used as a uniqueness theorem or as a substitute for the measured data supporting the thesis claims. The Supplement 3.6.5 comparison of logical to physical error rates is an empirical comparison; the skeptic's arithmetic inconsistency (j+_L at 0.49% versus a T2-derived physical bound near 0.36%) would be a correctness concern if verified, but it does not constitute a circular reduction. Overall, no load-bearing step reduces by construction to its own inputs.

Assumptions & free parameters 1 free parameters · 4 assumptions · 0 invented entities

The thesis relies on standard QEC assumptions (local, uncorrelated errors below threshold; stabilizer measurements are projective and QND; dispersive readout assignment errors are small). It also introduces one fitted model parameter (CZ leakage L1) to explain the observed error-detection rate in Chapter 3, and assumes single-qubit gate errors are negligible when extracting logical readout fidelity.

free parameters (1)

L1 (leakage per CZ gate) = ~5% (fitted)
Chapter 3 Supplement Model 5 treats L1 as a free parameter, assumed equal for all CZ gates, to match the measured post-selected fraction P(n); the authors explicitly state this is not an accurate measurement.

assumptions (4)

domain assumption A single fault in a logical operation either produces a non-trivial syndrome or a detectable outgoing error (fault-tolerance definition).
Used in Chapter 3 Section 3.1 and Supplement 3.6.7 to justify post-selection; states the error model is restricted to single local faults.
domain assumption Stabilizer measurements are projective and quantum non-demolition enough that post-selection removes errors without changing the logical state.
Chapter 3 Methods and Results; this is the basis for repetitive error detection.
ad hoc to paper Errors are dominated by local, Markovian decoherence plus a single fitted CZ leakage rate L1; correlated errors from residual ZZ and measurement are included only partially.
Supplement 3.6.14, Model 5; L1 assumed equal for all CZ gates and fitted to match P(n), explicitly labeled a free parameter.
domain assumption Single-qubit gate errors are negligible compared with data-qubit readout errors when extracting logical assignment fidelity.
Supplement 3.6.11 states this assumption to justify the accurate FR_L extraction method.

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Cite this review

Pith. "Pith review of Surface-code Superconducting Quantum Processors: From Calibration To Logical Performance." pith.science (2026). https://pith.science/paper/LMIYBDIQ

@misc{pith2026250417082,
  author       = {Pith},
  title        = {Pith review of: Surface-code Superconducting Quantum Processors: From Calibration To Logical Performance},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LMIYBDIQ}},
  note         = {Machine review of arXiv:2504.17082}
}

read the original abstract

Current quantum processors are fragile, noisy and fairly limited in both quantity and quality with tens of qubits and physical error rates of around 10^-3. To realize practical quantum applications, however, error rates need to be below 10^-15 across millions of qubits. To bridge this gap and fully harness the potential of quantum computers, quantum error correction (QEC) is essential. QEC codes are designed to protect quantum information by redundantly encoding it onto multiple physical qubits. This encoding allows for the detection and correction of local errors affecting individual qubits, e.g., through stabilizer measurements. Importantly, if the physical error rates are below a specific threshold, QEC codes can exponentially suppress logical error rates by increasing the number of physical qubits involved. This is essential for achieving fault-tolerant computations, which are key to unlocking the full potential of quantum computers. The work presented in this thesis focuses on the implementation and optimization of small-scale QEC experiments using the surface code and flux-tunable superconducting qubits (Transmons). It addresses several key challenges: enhancing two-qubit gate fidelity in Surface-4 (Chapter 2), implementing an error-detection code with Surface-7 (Chapter 3), automating the calibration and benchmarking of the building blocks in Surface-17 (Chapter 4), reducing leakage into higher excited states with leakage reduction units (Chapter 5), assessing and enhancing the performance of logical qubits (Chapters 7 and 8).

Figures

Figures reproduced from arXiv: 2504.17082 by the authors.

**Figure 1.1.** A full-stack quantum computer consists of multiple layers that must work together to implement a superconducting quantum computer. Various startups within the Delft quantum ecosystem contribute to different layers of this stack. The figure also highlights the goals, tasks, and challenges associated with each layer. A detailed discussion of these layers is provided in the main text. This thesis focuses on calibratio… view at source ↗

**Figure 1.2.** Energy levels of QHO and transmon as a function of the superconducting phase, . (a) Circuit diagram of a QHO consisting of an inductor and a capacitor. (b) Energy potential and eigenstates of the QHO, showing evenly spaced energy levels (h! ) characteristic of a QHO. (c) Circuit diagram of a transmon qubit, composed of a Josephson Junction shunted with a capacitance. (d) Energy potential and eigenstates of the trans… view at source ↗

**Figure 1.3.** Single-qubit gates and DRAG pulses. (a) The transmon qubit approximated as a two-level system, showing coherent qubit rotations on the Bloch sphere using microwave drives at the transition frequency . An gate excites the qubit from the ground state 0 to the excited state 1 . (b) Due to the weak anharmonicity of the transmon, pulse imperfections can cause leakage to higher states, such as 2 , and induce phase errors … view at source ↗

Figures from the paper (95 more)

**Figure 1.4.** Figure 1.4: Flux-tunable transmons and flux-based two-qubit gates (a) Circuit diagram of a flux-tunable transmon featuring a SQUID loop shunted with a capacitor and controlled by an external flux, ext. (b) Transition frequencies, 01=h and 02=h, as a function of the external flux…

**Figure 2.1.** Figure 2.1: Numerical simulation of an ideal SNZ pulse (infinite bandwidth and time resolution) [PITH_FULL_IMAGE:figures/full_fig_p038_2_1.png]

**Figure 2.2.** Figure 2.2: Calibration of the SNZ pulse for pair Q -QM2 and comparison to simulation. (a) 2 -state population of QM2 as a function of the amplitude and duration of a unipolar square pulse making 11 interact with 02 . (b,c) Landscapes of conditional phase 2Q and leakage estimate…

**Figure 2.3.** Figure 2.3: (a,b) Landscapes of the leakage estimate [PITH_FULL_IMAGE:figures/full_fig_p041_2_3.png]

**Figure 2.4.** Figure 2.4: Best SNZ CZ gate performance achieved from a single run of 2QIRB. (a) Refer [PITH_FULL_IMAGE:figures/full_fig_p043_2_4.png]

**Figure 2.5.** Figure 2.5: (a) Transition frequencies from 00 to levels ij in the one- and two-excitation manifold for transmon pair Q -QM2 as a function of magnetic flux through the SQUID loop of QM2, normalized to the flux quantum . Insets: Zoom-ins to the avoided crossings in the (left) two…

**Figure 2.6.** Figure 2.6: Comparison of conventional NZ and SNZ pulses for CZ gates. (a) Conventional NZ [PITH_FULL_IMAGE:figures/full_fig_p046_2_6.png]

**Figure 2.7.** Figure 2.7: Schematic comparison of the trajectory of level populations in the two-excitation [PITH_FULL_IMAGE:figures/full_fig_p047_2_7.png]

**Figure 2.8.** Figure 2.8: Optical image of the device, zoomed in to the four transmons used in this study and [PITH_FULL_IMAGE:figures/full_fig_p048_2_8.png]

**Figure 2.9.** Figure 2.9: Characterization of single-qubit gate infidelity [PITH_FULL_IMAGE:figures/full_fig_p050_2_9.png]

**Figure 2.10.** Figure 2.10: Time-domain characterization of the 11 - 02 and (c,d) 11 - 20 interactions for pair Q -QM1. (a,b) Landscapes of (a) ground-state population | i of Q and (b) total excited-state population 1 | i of QM1 as a function of the amplitude and duration of a unipolar square …

**Figure 2.11.** Figure 2.11: Extracted residual ZZ coupling between all pairs of qubits at their bias points. We report the frequency shift in one qubit (named echo qubit) when the computational state of another qubit (named control qubit) is shifted from 0 to 1 . An alternative way to evidence…

**Figure 2.12.** Figure 2.12: Comparison by 2QIRB of the fidelity and leakage of SNZ CZ versus idling (for [PITH_FULL_IMAGE:figures/full_fig_p052_2_12.png]

**Figure 2.13.** Figure 2.13: Error budgets for infidelity (a) and leakage (b) obtained by a numerical simulation (as in [94]) of the QM2-Q SNZ CZ gate with parameters in [PITH_FULL_IMAGE:figures/full_fig_p053_2_13.png]

**Figure 2.14.** Figure 2.14: Numerical simulation (using model E and pair [PITH_FULL_IMAGE:figures/full_fig_p054_2_14.png]

**Figure 3.1.** Figure 3.1: Surface-7 quantum processor and initialization of logical cardinal states. (a) Distance-two surface code. (b) Optical image of the quantum hardware with added false-color to emphasize different circuit elements. (c-f) Estimated physical density matrices, , after targ…

**Figure 3.2.** Figure 3.2: Arbitrary logical-state initialization and measurement in the logical cardinal bases. (a) Assembly of data-qubit measurements used to evaluate logical operators , and with additional error detection. (d) Initialization of logical states using the procedure described …

**Figure 3.3.** Figure 3.3: Logical gates and their characterization. (a, b) General gate-by-measurement schemes realizing arbitrary rotations around the (a) and (b) axis of the Bloch sphere. (c) Process tomography experiment of the gate. Input cardinal logical states are initialized using the …

**Figure 3.4.** Figure 3.4: Repetitive error detection using pipelined and parallel stabilizer measurement schemes. (a, b) Gate sequences used to implement the pipelined (a) and parallel (b) stabilizer measurement schemes. Gate duration is 20 ns for single-qubit gates, 60 ns for controlled-Z (…

**Figure 3.5.** Figure 3.5: Residual ZZ-coupling matrix. Measured residual ZZ coupling between all transmon pairs at the bias point (their simultaneous flux sweetspot [93]). Each matrix element denotes the frequency shift that the target qubit experiences due to the spectator qubit being in the…

**Figure 3.6.** Figure 3.6: Characterization of the assignment fidelity of -type parity checks. (a) D1 D3, (b) ∗ D1 D2 D3 D4, and (c) D2 D4 parity checks implemented using A , A , and A , respectively. Each parity check is benchmarked by preparing the relevant data qubits in a computational sta…

**Figure 3.7.** Figure 3.7: Full set of logical states measured in the logical process tomography procedure. Measured input and output logical states for each logical gate. Each state is measured using the procedure described in the Methods [PITH_FULL_IMAGE:figures/full_fig_p072_3_7.png]

**Figure 3.8.** Figure 3.8: Stabilization of logical cardinal states by repetitive error detection using the pipelined and parallel schemes. From left to right, the stabilized logical states are 0 , 1 , + and j . For each logical state, the top panel shows the evolution of the relevant logical …

**Figure 3.9.** Figure 3.9: Logical error probability versus number of error detection cycles. Logical error probability after cycles of error detection for states 0 , 1 (a) and + , j (b) measured using the pipelined scheme. For comparison, the grey dashed curves in (a) and (b) correspond to th…

**Figure 3.10.** Figure 3.10: Probability flow diagram for physical qubit readout. Please see text for the definition of all variables shown. The characterization of physical qubit readout robust to initialization errors determines the probabilities within the dashed box. Evidently, we want to q…

**Figure 3.11.** Figure 3.11: Probability flow diagram for logical readout. Please see text for the definition of all variables shown. The characterization of logical qubit readout robust to initialization errors determines the probabilities within the dashed box. The probability for states outs…

**Figure 3.12.** Figure 3.12: Experimental data-qubit assignment probability matrix. Each element of gives the experimental probability of measuring outcome string ( D1; mD2; mD3; mD4) (varying across rows) when performing simultaneous measurement of the data qubits prepared in D1 D2 D3 D4 , 2 …

**Figure 3.13.** Figure 3.13: Signature of transmon leakage in experimental data. Single-shot readout histograms obtained at cycle over all shots (red) and the post-selected shots based on detecting no error in any cycles up to (blue) for D (left), D (middle) and A (right) and at cycle = 1 (top …

**Figure 3.14.** Figure 3.14: Simulation of error-detection rate. Post-selected fraction as a function of the number of error-detection cycles for 0 . The experimental (blue dots) is compared to numerical simulation under various models (solid curves). (a) Simulated obtained by incremental addit…

**Figure 3.15.** Figure 3.15: Simulated post-selected fraction. Post-selected fraction of [PITH_FULL_IMAGE:figures/full_fig_p083_3_15.png]

**Figure 4.1.** Figure 4.1: Optical image of the 17-transmon device (Uran). False colors are added to highlight various essential circuit components of the device (see legend). Detailed description of each component is provided in the main text. Aluminum wirebonds at corners and edges are intro…

**Figure 4.2.** Figure 4.2: Device layout and overview of the achieved performance. (a) Device layout showing the connectivity (black lines) between data and ancilla qubits. The color of the plaquettes indicates that this device is purposely designed to implement a distance-three surface code.…

**Figure 4.3.** Figure 4.3: Fluctuations in device coherence of various 17-qubit devices fabricated with similar recipes. The cumulative distribution of the individually measured device coherence metrics: in (a), in (c), and ∗ in (d) extracted in various cooldowns. Vertical dashed lines indicat…

**Figure 4.4.** Figure 4.4: Frequency trimming of readout resonators using two techniques: wire-bonding (a), and Shoelace (e). The feedline transmission, 21 , is shown before (b) and after (d) wirebonding to mitigate the frequency overlap between qubits X and Z in device Aurelius. Characteriza…

**Figure 4.5.** Figure 4.5: Qubit frequency targeting in Maximus before and after laser annealing. (a) Measured qubit frequencies at bias point (simultaneous flux sweetspot) before and after laser annealing, in comparison with the ideal target frequencies. These measured frequencies are extract…

**Figure 4.6.** Figure 4.6: Characterization and impact of microwave crosstalk in Uran. (a) The measured 17 17 microwave crosstalk matrix reveals exceptionally low isolation, correlated with the positions of these crossovers, highlighted as colored squares in [PITH_FULL_IMAGE:figures/full_fig…

**Figure 4.7.** Figure 4.7: Single-qubit gate calibration and benchmarking. (a) GBT nodes for automatic calibration and benchmarking of single-qubit gates, assuming prior knowledge of qubit transition frequencies obtained through spectroscopy measurements. (b) A sample of the achieved single-q…

**Figure 4.8.** Figure 4.8: Mitigating of the impact of TLS on single-qubit gates by statically detuning the qubit frequency away from the interaction zone. and measurements at the sweetspot ( 2 = 0) in (a) and (c), and at a detuning of 2 = 100 MHz in (b) and (d). Orange color indicates the si…

**Figure 4.9.** Figure 4.9: Two-qubit gate calibration and benchmarking. (a) GBT graph nodes and dependencies are designed for automatic calibration of SNZ CZ gates. Overview of the achieved gate performance obtained by randomized benchmarking protocols for the standard SNZ flux pulse in (b), …

**Figure 4.10.** Figure 4.10: Flux arc calibration for qubit Z in the Uran device. (a) The quantum circuit involves embedding a fast square pulse into a Ramsey-like experiment before reading out the and components, by changing the final =2 rotation, of the Bloch sphere probing the qubit frequen…

**Figure 4.11.** Figure 4.11: 11 - 02 Chevron interaction of gate D -Z in device Uran. (a) Evolution of the 2 state population of qubit D and (b) the 1 state population of qubit Z as functions of the amplitude and duration of a unipolar square pulse applied to qubit D . This pulse effectively b…

**Figure 4.12.** Figure 4.12: Tmid calibration of the SNZ gate (a) The SNZ flux control parameters for the mid landscape include the main pulse amplitude A and the time mid between the two strong pulses within a 60 ns gate duration. Conditional oscillation experiments are conducted, and the two-…

**Figure 4.13.** Figure 4.13: AB calibration of the SNZ gate. (a) SNZ flux control parameters of the AB landscape are the main pulse amplitude A, and the intermediate amplitude B. Amplitudes A on the x axis (translated to frequency detuning through voltage-to-frequency conversion) and B on the y…

**Figure 4.14.** Figure 4.14: Fine-tuning of two-qubit gate performance. (a) Precision control of the twoqubit phase achieved through a conditional oscillation experiment by varying the amplitude B of the SNZ gate. The left panel illustrates phase errors when toggling the control qubit D betwe…

**Figure 4.15.** Figure 4.15: Parking optimization for minimizing spectator effects. (a) The computed transmon energy spectrum in the three-excitation manifold, denoted as , reveals avoided crossings when the spectator qubit D toggles between 0 and 1 . (b) The twoqubit phase, 2Q, and (c) phase …

**Figure 4.16.** Figure 4.16: Frequency trajectory of the SNZ gate Z -D . (a) Frequency trajectory, derived from flux pulse amplitudes and voltage-to-frequency conversion. Initially, the avoided crossing 11 - 02 overlaps with a TLS mode (red rectangle width is proportional to the coupling streng…

**Figure 4.17.** Figure 4.17: Instability of coherent operations with TLS. (a) Quantum circuit used to measure thee population loss of states 1 and 2 upon applying a unipolar flux pulse. The measured populations when qubit Z is initialized in states 1 (b), and 2 (c) as functions of the flux pul…

**Figure 4.18.** Figure 4.18: Asymmetric flux gate in presence of a strongly coupled TLS at the sweetspot. (a) Flux arc of the high-qubit qubit biased off-sweetspot (green point) and (b) Asymmetric flux pulse implementing two interaction points: orange on the left arm and darkorange on the righ…

**Figure 4.19.** Figure 4.19: A spectroscopy Cryoscope for the characterization of long-timescale flux pulse distortions. (a) Implementation of a 30 s flux pulse, while sliding a pulse with a 10 ns Gaussian envelope at various times t, to probe the qubit frequency. Due to various sources of dist…

**Figure 4.20.** Figure 4.20: Calibration and benchmarking of the DC CZ gate. (a) Flux arc and DC flux pulse (inset) implementing single unipolar interaction point (orange point) when higherfrequency qubit is intentionally biased off-sweetspot (green point). Note that the inset figure does not …

**Figure 4.21.** Figure 4.21: Calibration and benchmarking of the camelback CZ gate. (a) Flux arc and camelback flux pulse (inset) implementing two interaction points (orange point) in the same direction. The inset figure does not share any axis with the flux arc. Gate landscapes for (c) 2Q, and…

**Figure 4.22.** Figure 4.22: Calibration and benchmarking of readout using GBT. (a) Readout GBT nodes designed for autonomous calibration and benchmarking of single-qubit readout. (b) 2D coarse optimization of readout pulse frequency and amplitude to maximize the average readout assignment fide…

**Figure 4.23.** Figure 4.23: Impact of TLS on single-qubit readout. (a) Qubit frequency trajectory overlapping with a TLS mode during measurement. The qubit frequency experiences a Stark shift and is dephased at a rate denoted by (. (b) Suboptimal readout histograms with a significant probabil…

**Figure 4.24.** Figure 4.24: Multiplexed readout of ancilla and data qubits in (a), and (b), respectively, in device Uran. Experimental cross-fidelity matrices shown in (c), and (d). Readout assignment probabilities between ancilla and data qubits [102]. An end-to-end measurement, performed wit…

**Figure 4.25.** Figure 4.25: Mitigation of measurement-induced dephasing with Gaussian filtered Pulse effectively lowers dephasing rates on data qubits during ancilla measurements. (a) Standard readout square pulse, and (b) filtered Gaussian pulse with a sigma of 5 ns. The dephasing rate, , of …

**Figure 5.1.** Figure 5.1: Leakage reduction unit scheme. (a) Schematic for the driven transmonresonator system. A transmon (T, yellow) with three lowest-energy levels , , and is coupled to a readout resonator (R) with strength . The latter is coupled to a frequencymatched Purcell resonator …

**Figure 5.2.** Figure 5.2: Calibration of the leakage reduction unit pulse. (a) Pulse sequence used for LRU calibration. (b) Single-shot readout data obtained from the experiment. The blue, red and green areas denote , , and assignment regions, respectively. The mean (white dots) and 3 standar…

**Figure 5.4.** Figure 5.4: Repeated stabilizer measurement with leakage reduction. (a) Quantum circuit using ancilla A to measure the -type parity of data qubits D and D . The dashed box shows the frequency arrangement for two-qubit CZ gates. A CZ gate is performed by fluxing the higher-freque…

**Figure 5.5.** Figure 5.5: Circuit QED device. Optical image of the 17-transmon quantum processor, with added falsecolor to highlight different circuit elements. The shaded area indicates the three transmons used in this experiment [PITH_FULL_IMAGE:figures/full_fig_p136_5_5.png]

**Figure 5.6.** Figure 5.6: Repeated LRUs on D . Computational (top) and leakage (bottom) state population over repeated cycles of the circuit as shown. Transmon D is repeatedly put in superposition, controllably leaked with rate and measured. Measurement is followed by either idling (solid) …

**Figure 5.7.** Figure 5.7: Benchmarking of the weight-2 parity check. (a) Quantum circuit of the weight-2 -type parity check and bar plot of the average measured ancilla outcome for the different input computational states of the data-qubit register. Dashed bars show ideal average outcome: = …

**Figure 5.9.** Figure 5.9: Four state readout. (a) Single-shot readout data for the four lowest-energy transmon states , , and of A. Data are plotted for the first 3 10 from a total of 2 15 shots for each input state. The dashed lines show decision boundaries obtained from fitting a linear di…

**Figure 5.10.** Figure 5.10: Leakage reduction for and . (a, b) Transmon-resonator system level structure showing the relevant couplings for the -LRU (a) and -LRU (b). Each effective coupling, and , is mediated by its respective drive and and transmon-resonator coupling . (c, d) Readout data (2…

**Figure 5.11.** Figure 5.11: Higher leakage states of the ancilla qubit. Composition of ancilla leakage during the repeated stabilizer measurement of [PITH_FULL_IMAGE:figures/full_fig_p144_5_11.png]

**Figure 6.1.** Figure 6.1: A distance-3 QEC cycle. The quantum circuit illustrates the parallel scheme for a distance-3 surface code implemented in a 17-transmon device. Initially, the data qubit register is prepared in a product state of all 0’s. Subsequently, a Logical zero state, 0 , is ini…

**Figure 6.2.** Figure 6.2: Flux Dance of two-qubit gates in a distance-3 surface code. This fixed sequence illustrates the order of CZ gates employed to implement the eight and stabilizer measurements in a distance-3 surface code. Additional parking pulses (depicted by dashed circles) are nec…

**Figure 6.3.** Figure 6.3: Vertical calibration for a distance-3 surface code focuses on tuning and aligning three parallel CZ gates involved in each of the 8 steps, constituting the complete distance-3 flux dance. This improves two-qubit gate performance by mitigating flux crosstalk during s…

**Figure 6.4.** Figure 6.4: Horizontal calibration for a distance-3 surface code focuses on calibrating one type of parity check as a parallel block unit. This improves the overall parity check performance by mitigating coherent phase errors resulting from residual ZZ interactions between idlin…

**Figure 6.5.** Figure 6.5: Automatic calibration and benchmarking of stabilizer measurements with GBT. (a) The calibration graph illustrates nodes and dependencies for autonomously calibrating stabilizer measurements in 17-qubit devices. It initiates with the HC of parity checks as parallel b…

**Figure 6.6.** Figure 6.6: Horizontal calibration for X parity check. (a) Quantum circuit of the X parity check, performing four steps of 60 ns each to complete the full -type flux dance. The X - D two-qubit gate is omitted for simplicity. Following the X -D gate [highlighted in shaded blue], …

**Figure 6.7.** Figure 6.7: Weight-2 parity check assignment fidelity. (a) Quantum circuit of the weight-2 -type parity check. Characterization of the assignment fidelity of stabilizer measurements in (a) 1 2 , (b) 3 6 , (c) 8 9 , and (d) 7 4 , implemented using the X , Z , X , and Z qubits in …

**Figure 6.8.** Figure 6.8: Measured weight-4 parity check assignment fidelities of X , X , Z , and Z in Uran device. The extracted fidelities are 86 2%, 92 3%, 89 9%, and 92 3%, respectively, averaged across the 16 prepared data-qubit states. The reported values are corrected for residual exci…

**Figure 6.9.** Figure 6.9: Weight-2 Bell-state generation via stabilizer measurement assesses the backaction on data-qubit state by generating a Bell-state via weight-2 -type parity check and data-qubit tomography for Uran device in (a). The latter is conditioned on the ancilla outcome: = +1,…

**Figure 6.10.** Figure 6.10: Weight-4 Bell-state generation via stabilizer measurement. Reconstructed data-qubit density matrices resulting from weight-4 stabilizer measurements of X in (a), X in (a), Z in (a), and Z in (a) for Uran device. The extracted Bell state fidelities are 66 4%, 84 4%, …

**Figure 6.11.** Figure 6.11: Weight-2 parity check repeatability quantifies parity assignment errors and the disturbance on data qubits by measuring two back-to-back -type parity checks while initializing the data-qubit register in the 0 state. A dynamical decoupling sequence of gates on data q…

**Figure 6.12.** Figure 6.12: Measured weight-4 parity check repeatability for (a) Z , (b) X , (c) X , and (d) Z stabilizers. The obtained probabilities ( = +1) are 83 5%, 61 4%, 81 1%, and 80 9%, respectively. The extremely low value for the X stabilizer is attributed to a strong coupling to a …

**Figure 6.** Figure 6 [PITH_FULL_IMAGE:figures/full_fig_p161_6.png]

**Figure 6.14.** Figure 6.14: A bit-flip distance-3 surface code. (a) Device layout with flux-tunable transmons at vertices and fixed coupling resonator buses indicating nearest-neighbor connectivity. Shaded plaquettes and vertices are inactive in this experiment. (b) The qubit frequencies meas…

**Figure 6.15.** Figure 6.15: Error-detection fraction and accumulated leakage. (a) Initialization for one of 16 input states on the data qubits, followed by repeated -type parity checks to stabilize against bit-flip errors. (b) Error-detection probability, known as defect rate, illustrates the …

**Figure 6.** Figure 6 [PITH_FULL_IMAGE:figures/full_fig_p167_6.png]

**Figure 6.17.** Figure 6.17: Logical performance using various decoding strategies. (a) Logical fidelity of the approximated 0 state, obtained by averaging the logical decay of the 16 input states, as a function of QEC rounds. (b) for various decoders detailed in the main text. (c) QED post-sel…

**Figure 6.18.** Figure 6.18: Initial attempt for the realization of a distance-3 QEC code (a) QEC quantum circuit used to measure the stabilizers of Surface-17. (b) Defect probability as a function of the number of rounds for each stabilizer of the Surface-17 code. Several factors contributed t…

**Figure 7.1.** Figure 7.1: Surface-13 QEC experiment. (a) Device layout, with vertices indicating fluxtunable transmons, and edges denoting nearest-neighbor coupling via fixed-frequency resonators. Nine data qubits in a 3 3 array (labeled , dark gray) are subject to 4 -basis parity checks re…

**Figure 7.2.** Figure 7.2: (a) The measurement response of the 0 and 1 states in IQ space for data qubit , showing a projection line that connects the means of the two Gaussian peaks (black dotted line). (b) Edge weight as a function of projected voltage for soft and hard measurements; see Equ…

**Figure 7.3.** Figure 7.3: (a) Decoding graph showing different types of error mechanisms. The labels [PITH_FULL_IMAGE:figures/full_fig_p180_7_3.png]

**Figure 7.4.** Figure 7.4: (a) Our NN architecture, a variant of Ref. [ [PITH_FULL_IMAGE:figures/full_fig_p181_7_4.png]

**Figure 7.5.** Figure 7.5: Device characteristics. (a) Optical image of the 17-transmon device, with added false color to emphasize different circuit elements. The device is connected to a printed circuit board using aluminum wirebonds, visible at the edges of the image. (b) Measured qubit tra…

**Figure 7.6.** Figure 7.6: Parity check benchmarking. (a) Benchmarking of the assignment fidelity for four stabilizer measurements: 4 7 , 6 3 , 4 5 2 1 , and 9 9 5 6 . (b) The average defect rate as a function of QEC rounds for each of the four -basis stabilizers across the 16 input states. W…

**Figure 7.7.** Figure 7.7: Logical error rates of the NN decoders when given different inputs: the label [PITH_FULL_IMAGE:figures/full_fig_p187_7_7.png]

**Figure 7.8.** Figure 7.8: Logical performance of the NNs given the four input combinations and different [PITH_FULL_IMAGE:figures/full_fig_p189_7_8.png]

**Figure 7.9.** Figure 7.9: Evaluation runtime for the size-5 network with batch size = 1. The line corresponds [PITH_FULL_IMAGE:figures/full_fig_p190_7_9.png]

**Figure 7.10.** Figure 7.10: Calibration shots for experimental IQ voltages, shown for each ancilla prepared in [PITH_FULL_IMAGE:figures/full_fig_p196_7_10.png]

**Figure 7.11.** Figure 7.11: Logical fidelity using soft versus hard MWPM decoder for each round of the [PITH_FULL_IMAGE:figures/full_fig_p201_7_11.png]

**Figure 7.12.** Figure 7.12: Absolute difference in logical fidelity as a function of rounds, shown for each individual logical state preparation 0 (transparent) and on average across 16 states (opaque) for soft versus hard MWPM [PITH_FULL_IMAGE:figures/full_fig_p202_7_12.png]

**Figure 8.1.** Figure 8.1: Correlation matrix without and with LRU Stabilization of the logical zero state without (a) and with (b) LRU applied on high frequency qubits, D , D , D . The application of LRU extends the QEC cycle by 240 ns, with the Pij matrix in (b) showing reduced long-term cor…

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Analytic gradients for low-rank quantum optimal control
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A new gradient-based quantum control algorithm propagates only a low-rank factorization of the density matrix, giving analytic gradients and quadratic speedups over full master-equation simulations for high-purity protocols.

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arXiv

Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.

[1] [1]

H. Ali, J. F . Marques, O. Crawford, and J. Majaniemi,Reducing the error rate of a superconducting logical qubit using analog readout information , Physical Review Applied, Vol. 22, No. 4, Article 044031 (2024)

2024

[2] [2]

J. F . Marques , H. Ali , B. M. Varbanov, M. Finkel, H. M. Veen, S. L. M. van der Meer, S. Valles- Sanclemente, N. Muthusubramanian, M. Beekman, N. Haider, B. M. Terhal, and L. DiCarlo, All- Microwave Leakage Reduction Units for Quantum Error Correction with Superconducting Transmon Qubits, Physical Review Letters, Vol. 130, No. 25, Article 250602 (2023)

2023

[3] [3]

Vallés-Sanclemente, S

S. Vallés-Sanclemente, S. L. M. van der Meer, M. Finkel, N. Muthusubramanian, M. Beekman, H. Ali, J. F . Marques, C. Zachariadis, H. M. Veen, T. Stavenga, N. Haider, and L. DiCarlo, Post- fabrication frequency trimming of coplanar-waveguide resonators in circuit QED quantum proces- sors, Applied Physics Letters, Vol. 123, No. 3, Article 034004 (2023)

2023

[4] [4]

M. S. Moreira, G. G. Guerreschi, W. Vlothuizen, J. F . Marques, J. van Straten, S. P . Premaratne, X. Zou, H. Ali, N. Muthusubramanian, C. Zachariadis, J. van Someren, M. Beekman, N. Haider, A. Bruno, C. G. Almudever, A. Y . Matsuura, and L. DiCarlo, Realization of a quantum neural network using repeat-until-success circuits in a superconducting quantum p...

2023

[5] [5]

J. F . Marques, B. M. Varbanov, M. S. Moreira, H. Ali, N. Muthusubramanian, C. Zachariadis, F . Battistel, M. Beekman, N. Haider, W. Vlothuizen, A. Bruno, B. M. Terhal, and L. DiCarlo, Logical- qubit operations in an error-detecting surface code , Nature Physics, Vol. 18, No. 1, pp. 80-86 (2022)

2022

[6] [6]

Negîrneac , H

V. Negîrneac , H. Ali , N. Muthusubramanian, F . Battistel, R. Sagastizabal, M. S. Moreira, J. F . Marques, W. J. Vlothuizen, M. Beekman, C. Zachariadis, N. Haider, A. Bruno, and L. DiCarlo,High- Fidelity Controlled-Z Gate with Maximal Intermediate Leakage Operating at the Speed Limit in a Superconducting Quantum Processor, Physical Review Letters, Vol. 1...

2021

[7] [7]

Janneck, T

R. Janneck, T. S. Nowack, F . De Roose,H. Ali, W. Dehaene, P . Heremans, J. Genoe, and C. Rolin, Integration of highly crystalline C8-BTBT thin-ﬁlms into simple logic gates and circuits , Organic Electronics, Vol. 67, pp. 64-71 (2019)

2019

[8] [8]

H. Ali, M. Pirro, P . Poulichet, W. Cesar, F . Marty, I. Azzouz, M. Gnambodoe-Capochichi, E. Nefzaoui, T. Bourouina, Thermal aspects of a micro thermal conductivity detector for micro gas chromatogra- phy,s 2019 Symposium on Design, Test, Integration and Packaging of MEMS and MOEMS (DTIP), pp. 1-6, IEEE, (2019)

2019