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REVIEW 3 major objections 5 minor 1 cited by

RoCE BALBOA: Service-enhanced Data Center RDMA for SmartNICs

T0 review · 3 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read RoCE BALBOA is an open-source FPGA RDMA stack that claims full RoCE v2 compatibility at 100G with performance comparable to commercial NICs, and uses its openness to put protocol enhancements and application offloads directly on the…

desk verdict An open, genuinely useful FPGA RoCE stack with real switched-network measurements; just don't take 'fully RoCE-v2 compatible' literally — it's tested only for one-sided WRITE/READ. read the letter →

arxiv 2507.20412 v1 pith:PUWKRPIE submitted 2025-07-27 cs.AR cs.NI

Maximilian Jakob Heer , Benjamin Ramhorst , Yu Zhu , Luhao Liu , Zhiyi Hu , Jonas Dann , Gustavo Alonso This is my paper · ORCID
classification cs.ARcs.NI
keywords RDMARoCEv2FPGASmartNICnetworkstackdatapathoffloadGPUDMAdeeppacketinspection
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper sets out to show that a fully open, customizable RDMA endpoint for FPGAs can be built to the RoCE v2 standard and can hold its own against commercial NICs in a switched 100G data center network. If true, it would give researchers a line-rate platform for building SmartNICs and in-network accelerators without being locked into closed silicon. The paper demonstrates the payoff with two kinds of extension: protocol-level services (AES encryption and machine-learning deep packet inspection) and application-level compute (recommender-system preprocessing) executed as data streams through the NIC, including direct DMA to a GPU. The central claim is that performance comparable to commercial NICs does not require giving up openness and extensibility.

What carries the argument

The load-bearing mechanism is a 512-bit-wide AXI-stream packet processing pipeline clocked at 250 MHz, giving 128 Gbps of internal bandwidth against the 100G line rate, with per-queue-pair tables (connection, PSN state, and MSN sequence control) that let the stack track, accept, drop, or retransmit packets in hardware. Around that pipeline sit an HBM-backed retransmission buffer, an ACK-clocked flow-control and crediting mechanism, a specialized ICRC checksum block that handles full, partial, and 32-bit AXI beats in parallel, and defined slots for exchangeable on-datapath and parallel-path services. These slots are what carry the paper's extensions: AES-ECB encryption on the datapath, an ML-based deep packet inspection module on a parallel path, and user logic that can forward or transform payloads before DMA to host or GPU memory.

What would settle it

Run a standards-level RoCE v2 interoperability test in which BALBOA exchanges two-sided SEND/RECV messages with a commercial NIC, forces duplicate, out-of-order, and lost packets to check NAK and retransmission behavior, and stresses multiple QPs under congestion; if any of those exchanges fails or the link no longer stays at line rate, the full-compatibility claim falls.

Watch

Extended reading notes

Core claim

In the paper's own terms, RoCE BALBOA is a fully RoCE-v2 compatible, 100G-capable RDMA network stack for data center FPGAs that interoperates with commercial NICs through switched networks and offers latency and throughput comparable to those NICs. It is built as a customizable packet-processing pipeline with exchangeable on-datapath and parallel-path service slots, allowing protocol enhancements to be inserted without breaking line rate. Using this design, the paper shows RDMA WRITE and RDMA READ both saturate a 100G link in FPGA-to-FPGA and FPGA-to-commercial-NIC flows, and demonstrates on-datapath AES encryption that adds only 25 ns of latency, an ML deep-packet-inspection service whose inference time is hidden by the pipeline, and a recommender preprocessing pipeline that streams data straight to GPU memory at up to 8500 MB/s versus roughly 700 MB/s for a CPU implementation.

Load-bearing premise

Full RoCE-v2 conformance is assumed from a narrow test set: only one-sided RDMA WRITE and RDMA READ were measured between BALBOA and one brand of commercial NIC through a switch, leaving two-sided SEND and RECV, NAK generation, and duplicate or out-of-order PSN recovery untested.

Editorial extensions

If this is right

  • If the compatibility claim holds, researchers can use an open FPGA stack as a drop-in RDMA endpoint for data center experiments, including mixed deployments with commercial NICs and switches.
  • Protocol security gaps in RoCE v2, such as missing encryption and weak access control, can be patched at the NIC datapath while preserving CPU and OS bypass.
  • Data preprocessing for GPU workloads can move out of the CPU entirely: the paper's recommender pipeline runs at line rate on the NIC and writes directly to GPU memory.
  • New congestion control and network services, such as DCQCN or TIMELY-style schemes, can be implemented and evaluated in hardware without waiting for vendor NIC firmware.
  • The small resource footprint (roughly 4% of FPGA LUTs in the report) leaves room for multiple user offloads alongside the stack in a single accelerator.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper's compatibility evidence is limited to one-sided RDMA WRITE and READ in a narrow test matrix; if two-sided SEND/RECV, NAK generation, and out-of-order or duplicate PSN recovery are also conformant, the stack becomes a credible alternative to commercial NICs for a much wider class of systems research.
  • Because the stack is open and the service slots are AXI-stream based, the same architecture could host other line-rate functions the paper does not implement, such as data compression, parsing, or transparent traffic monitoring, with the DPI and encryption modules as templates.
  • A testable extension is to benchmark the DPI model against a live attack replay or against NVMe-over-RDMA traffic carrying real malware, rather than the CSV/PNG/TXT versus executable training distributions used here.
  • If adopted as a platform, the open stack could make congestion-control and load-balancing proposals comparable across labs, since every group would run the same hardware datapath rather than vendor-specific emulation.
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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper presents RoCE BALBOA, an open-source FPGA-based RDMA stack targeting 100G data centers. The stack implements the RoCE v2 protocol in Reliable Connection mode, focusing on one-sided operations (RDMA WRITE and RDMA READ), and includes retransmission buffering, flow control, and an ICRC pipeline. The authors deploy BALBOA on AMD Alveo U55C FPGAs in a switched cluster and report throughput and latency results for FPGA-to-FPGA, FPGA-to-Mellanox, and Mellanox-to-Mellanox configurations. They also demonstrate protocol enhancements (AES encryption and ML-based deep packet inspection) and an offloaded DLRM preprocessing pipeline with direct-to-GPU DMA, and report resource utilization. The central claim is that BALBOA is a fully RoCE-v2-compatible, 100G-capable, open-source stack with performance comparable to commercial NICs.

Significance. The open-source release, the real-cluster switched-network evaluation, and the direct comparison against Mellanox ConnectX-5 NICs are concrete strengths. The tested one-sided RDMA WRITE and READ operations achieve line rate and interoperate with a commercial NIC through a Cisco switch, which is a meaningful step for FPGA-based RDMA research. The on-datapath service slots and the DLRM preprocessing use case demonstrate a useful design pattern for SmartNICs. The main caveat is that the unconditional 'fully RoCE-v2 compatible' claim is broader than the tested subset; if the claim is properly scoped or the missing conformance tests are added, this would be a valuable open platform for SmartNIC and in-network computing research.

major comments (3)
  1. [Abstract, Section 1, Section 2, Section 6.1] The abstract and the contribution list in Section 1 describe RoCE BALBOA as 'fully RoCE-v2 compatible' without qualification, but Section 2 states that 'BALBOA concentrates on one-sided operations,' and Section 6.1 evaluates only RDMA WRITE and RDMA READ against a Mellanox NIC through a switch. No tests are reported for two-sided SEND/RECV, ATOMIC operations, NAK generation for invalid or out-of-order PSNs, retransmission recovery under forced packet loss, or multi-QP error behavior. Because the headline interoperability claim is load-bearing, this scope gap must be addressed: either add conformance tests for these RC service behaviors, or explicitly re-scope the claim to 'one-sided RC operations' in the abstract and contribution list.
  2. [Section 6.4.2] The DPI use case reports detection rates of 97.83% for whole packets and 89.35% for partially embedded executables, but does not report the false positive rate, the dataset size, or the decision threshold. Without these numbers, the claim that the service offers a 'highly effective and fine-grained differentiation policy' is not fully supported. Please provide a confusion matrix or at minimum the false positive rate and the composition of the test set.
  3. [Section 6.3 and Section 4.1] The abstract claims BALBOA is 'scalable up to hundreds of queue-pairs' and Section 4.1 states that the default tables support 500 QPs, but Section 6.3 does not report the number of QPs used in the multi-QP scaling experiment or the QP count at which fairness degrades. Please state the number of concurrent QPs tested and, if possible, show scaling up to at least 100 QPs to substantiate the abstract's claim.
minor comments (5)
  1. [Section 6.1] In Figure 4a and 4c, the Mellanox-to-Mellanox throughput curves are plotted without the P5/P95 percentiles shown for the other curves; please clarify whether this is intentional or add the variability information.
  2. [Section 8.2] The text states the local PCIe path is limited to approximately 70 Gbps (8500 MB/s), but 8500 MB/s equals approximately 68 Gbps; please correct the rounding for consistency.
  3. [Section 6.4.2] The sentence referring to 'the native false positive rate of flagging acceptable payloads' is incomplete because the actual false positive rate is never reported; please provide the number or remove the reference.
  4. [Section 5.1.2] The 44 ns inference latency for the DPI module is given, but the FPGA clock frequency is not stated; please specify the clock frequency to make the latency number reproducible.
  5. [References] Some references have formatting issues, notably reference [22] which contains a stray backtick in the author name; a careful proofread of the reference list is needed.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: central claims are anchored to external benchmark hardware, and self-cited components are supporting artifacts rather than fitted inputs.

full rationale

RoCE BALBOA's central claims—100G throughput, latency and throughput comparable to commercial NICs, and switched-network interoperability—are established by measurements against external hardware (Mellanox ConnectX-5 NICs, a Cisco Nexus 9000 switch, and a public research cluster) rather than by construction from the stack's own definitions. No parameter is fitted to the compared data, and no reported quantity is an algebraic restatement of an input. The ICRC pipeline reimplements concepts from the non-self-cited reference [60], and the flow-control, retransmission, and packet-processing descriptions are architectural rather than derived from self-cited results. The AES core (from the authors' repository), the DPI module [31], and the preprocessing pipeline [82] are self-cited or self-hosted components, but their latency, throughput, and detection numbers are measured in the present system and they are not used to define BALBOA's core performance, so these self-citations are not load-bearing. The one significant scope caveat—the abstract's and Section 1's 'fully RoCE-v2 compatible' wording versus Section 2's statement that BALBOA 'concentrates on one-sided operations' and Section 6.1's WRITE/READ-only interop tests—is a correctness and claim-scope concern, not a circular derivation, because the tested compatibility evidence is external and does not presuppose the conclusion.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

No numerical free parameters are fitted to support the central claims; the scorecard rests on experimental measurements. The assumptions listed here are domain assumptions about protocol scope, IP core correctness, ML generalization, test topology, and encryption semantics, none of which is validated beyond the paper's specific setup.

assumptions (5)
  • domain assumption The tested subset of RoCE v2, RC mode with one-sided RDMA WRITE and READ, is sufficient evidence for the 'fully RoCE-v2 compatible' claim.
    Invoked in the abstract and Section 1, evaluated only in Section 6.1. Section 2 explicitly says BALBOA concentrates on one-sided operations, so full protocol conformance is not established.
  • domain assumption AMD IP cores (CMAC, XDMA) and the Coyote v2 shell behave as specified and provide error-free 100G and PCIe transport.
    The evaluation in Section 6 depends on these cores; any undisclosed IP bug or configuration quirk would affect the measurements.
  • domain assumption The hls4ml-synthesized DPI classifier generalizes from its training distribution to real datacenter RDMA payloads.
    Section 5.1.2 and Section 6.4.2 report detection rates for CSVs, PNGs, TXTs, and malware executables, but no false positive rate or real-traffic validation is given.
  • domain assumption The public HACC cluster and its switch topologies are representative of production data center conditions.
    Section 6 uses one subnet and a two-tier fat-tree. Results may differ under different congestion levels, MTU settings, or traffic patterns.
  • domain assumption AES-ECB encryption on the payload datapath is semantically acceptable for the service use case without protocol-level session or key management.
    Section 5.1.1 inserts an AES core with keys exchanged out of band. Standard commercial endpoints cannot decrypt the encrypted payload, so the enhancement is not a drop-in protocol extension.

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Cite this review

Pith. "Pith review of RoCE BALBOA: Service-enhanced Data Center RDMA for SmartNICs." pith.science (2026). https://pith.science/paper/PUWKRPIE

@misc{pith2026250720412,
  author       = {Pith},
  title        = {Pith review of: RoCE BALBOA: Service-enhanced Data Center RDMA for SmartNICs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/PUWKRPIE}},
  note         = {Machine review of arXiv:2507.20412}
}
read the original abstract

Data-intensive applications in data centers, especially machine learning (ML), have made the network a bottleneck, which in turn has motivated the development of more efficient network protocols and infrastructure. For instance, remote direct memory access (RDMA) has become the standard protocol for data transport in the cloud as it minimizes data copies and reduces CPU-utilization via host-bypassing. Similarly, an increasing amount of network functions and infrastructure have moved to accelerators, SmartNICs, and in-network computing to bypass the CPU. In this paper we explore the implementation and deployment of RoCE BALBOA, an open-source, RoCE v2-compatible, scalable up to hundreds of queue-pairs, and 100G-capable RDMA-stack that can be used as the basis for building accelerators and smartNICs. RoCE BALBOA is customizable, opening up a design space and offering a degree of adaptability not available in commercial products. We have deployed BALBOA in a cluster using FPGAs and show that it has latency and performance characteristics comparable to commercial NICs. We demonstrate its potential by exploring two classes of use cases. One involves enhancements to the protocol for infrastructure purposes (encryption, deep packet inspection using ML). The other showcases the ability to perform line-rate compute offloads with deep pipelines by implementing commercial data preprocessing pipelines for recommender systems that process the data as it arrives from the network before transferring it directly to the GPU. These examples demonstrate how BALBOA enables the exploration and development of SmartNICs and accelerators operating on network data streams.

Figures

Figures reproduced from arXiv: 2507.20412 by the authors.

Figure 1
Figure 1. Overview of RoCE BALBOA, consisting of the customizable 100G RoCE packet processing pipelines and stack [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 3
Figure 3. Building blocks of BALBOA: ➀ - ACK-clocked flow control, ➁ - Retransmission logic, ➂ - ICRC pipeline outs or PSN sequence errors, the required payload should not be requested from the host to avoid an additional PCIe transaction with the incurred latency overhead. Instead, all transmitted payloads need to be held in card memory until remote acknowledgement of reception. Within this module ( [PITH_FULL_IMAGE:figures… view at source ↗
Figure 4
Figure 4. Performance evaluation of RoCE BALBOA in a switched 100G datacenter network. Displayed are average results over [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
Figures from the paper (6 more)
Figure 5
Figure 5. Figure 5: Breakdown of the end-to-end latency for various [PITH_FULL_IMAGE:figures/full_fig_p009_5.png]
Figure 8
Figure 8. Figure 8: Throughput and latency with and without deployed [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]
Figure 7
Figure 7. Figure 7: Comparison of AES implementations residing on [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]
Figure 9
Figure 9. Figure 9: Visualization of the three described testing setups [PITH_FULL_IMAGE:figures/full_fig_p011_9.png]
Figure 10
Figure 10. Figure 10: Throughput of ML preprocessing in BALBOA [PITH_FULL_IMAGE:figures/full_fig_p012_10.png]
Figure 11
Figure 11. Figure 11: Latency of ML preprocessing in BALBOA with [PITH_FULL_IMAGE:figures/full_fig_p012_11.png]

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Oasis: Hiding the Cost of Querying Parquet Files in the Datapath

    cs.DB 2026-08 accept novelty 6.0 of 10

    Moving Parquet decoding onto a SmartNIC in the network datapath overlaps scan cost with query execution and almost doubles DuckDB TPC-H throughput in the best measured case.

Reference graph

Works this paper leans on

84 extracted references · 78 canonical work pages · cited by 1 Pith paper

  1. [1]

    IEEE Std 802.3-2012 (Revision to IEEE Std 802.3-2008) (2012), 1–3747

    Ieee standard for ethernet. IEEE Std 802.3-2012 (Revision to IEEE Std 802.3-2008) (2012), 1–3747

    2012

  2. [2]

    GitHub, https://github.com/ facebookresearch/dlrm

    Deep learning recommendation model for personalization and rec- ommendation systems:, 2024. GitHub, https://github.com/ facebookresearch/dlrm

    2024

  3. [3]

    https://docs.nvidia.com/networking/display/ nvidia-bluefield-3-dpu-controller-user-manual.pdf

    Nvidia bluefield-3 dpu controller user manual, 2024. https://docs.nvidia.com/networking/display/ nvidia-bluefield-3-dpu-controller-user-manual.pdf

    2024

  4. [4]

    K., A MARO , E., A MIT, N., H UNHOFF , E., Y ELAM , A., AND ZELLWEGER , G

    AGUILERA , M. K., A MARO , E., A MIT, N., H UNHOFF , E., Y ELAM , A., AND ZELLWEGER , G. Memory disaggregation: why now and what are the challenges. SIGOPS Oper. Syst. Rev. 57, 1 (June 2023), 38–46

    2023

  5. [5]

    K., A MIT, N., C ALCIU , I., D EGUILLARD , X., GANDHI , J., N OVAKOVI ´C, S., R AMANATHAN , A., S UBRAHMANYAM , P., SURESH , L., T ATI, K., V ENKATASUBRAMANIAN , R., AND WEI, M

    AGUILERA , M. K., A MIT, N., C ALCIU , I., D EGUILLARD , X., GANDHI , J., N OVAKOVI ´C, S., R AMANATHAN , A., S UBRAHMANYAM , P., SURESH , L., T ATI, K., V ENKATASUBRAMANIAN , R., AND WEI, M. Remote regions: a simple abstraction for remote memory. In 2018 USENIX Annual Technical Conference (USENIX ATC 18) (Boston, MA, July 2018), USENIX Association, pp. 775–787

    work page 2018

  6. [6]

    K., A MIT, N., C ALCIU , I., D EGUILLARD , X., GANDHI , J., S UBRAHMANYAM , P., SURESH , L., TATI, K., V ENKATA - SUBRAMANIAN , R., AND WEI, M

    AGUILERA , M. K., A MIT, N., C ALCIU , I., D EGUILLARD , X., GANDHI , J., S UBRAHMANYAM , P., SURESH , L., TATI, K., V ENKATA - SUBRAMANIAN , R., AND WEI, M. Remote memory in the age of fast networks. In Proceedings of the 2017 Symposium on Cloud Computing (New York, NY , USA, 2017), SoCC ’17, Association for Computing Machinery, p. 121–127

    work page 2017

  7. [7]

    K., K EETON , K., N OVAKOVIC , S., AND SINGHAL , S

    AGUILERA , M. K., K EETON , K., N OVAKOVIC , S., AND SINGHAL , S. Designing far memory data structures: Think outside the box. In Proceedings of the Workshop on Hot Topics in Operating Systems (New York, NY , USA, 2019), HotOS ’19, Association for Computing Machinery, p. 120–126

    work page 2019

  8. [8]

    Amd embedded rdma enabled nic v4.2, 2024

    AMD. Amd embedded rdma enabled nic v4.2, 2024. https://docs. amd.com/viewer/book-attachment/pALa6__dFBrEQ5VQoJ9ygg/ gP6nwK9Yi85wq3xZ4KyqZw-pALa6__dFBrEQ5VQoJ9ygg

    work page 2024

Show all 84 references
  1. [9]

    Dma/bridge subsystem for pci express product guide (pg195),

    AMD . Dma/bridge subsystem for pci express product guide (pg195),

  2. [10]

    Ultrascale+ devices integrated 100g ethernet subsystem logicore ip product guide (pg203), 2024

    AMD. Ultrascale+ devices integrated 100g ethernet subsystem logicore ip product guide (pg203), 2024. https://docs.amd.com/r/en-US/ pg203-cmac-usplus

    2024

  3. [11]

    ASSOCIATION , I. T. Roce v2 specification, 2014. https://www. infinibandta.org/ibta-specification/

    2014

  4. [12]

    Ocp summit 2024: The open future of networking hardware for ai, 2024

    BAGGA , J., F ANG , T., K HARE , S., M OELLER , O., P ROVINE , J., SUNKAD , R., W ANG , X., W U, L., AND ZHOU , R. Ocp summit 2024: The open future of networking hardware for ai, 2024. Accessed on April 8, 2025

    2024

  5. [13]

    S., A GRAWAL , A., A TTRE , K

    BAI, W., A BDEEN , S. S., A GRAWAL , A., A TTRE , K. K., B AHL , P., BHAGAT, A., B HASKARA , G., B ROKHMAN , T., C AO, L., C HEEMA , A., C HOW, R., C OHEN , J., E LHADDAD , M., E TTE , V., F IGLIN , I., FIRESTONE , D., G EORGE , M., G ERMAN , I., G HAI , L., G REEN , E., G REE...

    2023

  6. [14]

    Scaling data ingestion for machine learning training at meta, Oct 2022

    BASANT , A. Scaling data ingestion for machine learning training at meta, Oct 2022. https:// engineering.fb.com/2022/09/19/ml-applications/ data-ingestion-machine-learning-training-meta/

    2022

  7. [15]

    Modyn: Data-centric machine learning pipeline orchestration

    BÖTHER , M., R OBROEK , T., G STEIGER , V., H OLZINGER , R., M A, X., T ÖZÜN , P., AND KLIMOVIC , A. Modyn: Data-centric machine learning pipeline orchestration. Proceedings of the ACM on Manage- ment of Data 3, 1 (2025), 1–30

    2025

  8. [16]

    Nvidia data center processing unit (dpu) architecture

    BURSTEIN , I. Nvidia data center processing unit (dpu) architecture. In 2021 IEEE Hot Chips 33 Symposium (HCS) (2021), pp. 1–20

    2021

  9. [17]

    A cloud- scale acceleration architecture

    CAULFIELD , A., C HUNG , E., P UTNAM , A., A NGEPAT, H., F OWERS , J., H ASELMAN , M., H EIL , S., H UMPHREY , M., K AUR, P., K IM, J.- Y., LO, D., M ASSENGILL , T., O VTCHAROV , K., P APAMICHAEL , M., WOODS , L., L ANKA , S., C HIOU , D., AND BURGER , D. A cloud- scale accele...

    2016

  10. [18]

    Demystifying datapath accelerator enhanced off-path smartnic

    CHEN , X., Z HANG , J., F U, T., S HEN , Y., M A, S., Q IAN , K., Z HU, L., S HI, C., Z HANG , Y., L IU, M., AND WANG , Z. Demystifying datapath accelerator enhanced off-path smartnic. In 2024 IEEE 32nd International Conference on Network Protocols (ICNP) (2024), pp. 1– 12

    2024

  11. [19]

    Hardware acceleration of compression and encryption in sap hana

    CHIOSA , M., M ASCHI , F., M ÜLLER , I., A LONSO , G., AND MAY, N. Hardware acceleration of compression and encryption in sap hana. Proc. VLDB Endow. 15, 12 (Aug. 2022), 3277–3291

    2022

  12. [20]

    Enabling communication with fpga-based network-attached accelerators for hpc workloads

    CHRISTGAU , S., E VERINGHAM , D., M IKOLAJCZAK , F., S CHELTEN , N., S CHNOR , B., S CHROETTER , M., S TABERNACK , B., AND STEIN - ERT, F. Enabling communication with fpga-based network-attached accelerators for hpc workloads. In Proceedings of the SC ’23 Work- shops of the In...

    2023

  13. [21]

    Enzian: an open, general, cpu/fpga platform for systems software research

    COCK , D., R AMDAS , A., S CHWYN , D., G IARDINO , M., T UROWSKI , A., H E, Z., H OSSLE , N., K OROLIJA , D., L ICCIARDELLO , M., M ART- SENKO , K., ACHERMANN , R., ALONSO , G., AND ROSCOE , T. Enzian: an open, general, cpu/fpga platform for systems software research. In Proce...

    2022

  14. [22]

    Securing InfiniBand networks with the bluefield-2 data processing unit

    DIAMOND ‘, N., G RAHAM , S., AND CLARK , G. Securing InfiniBand networks with the bluefield-2 data processing unit. iccws 17, 1 (Mar. 2022), 459–468

    2022

  15. [23]

    Fast inference of deep neural networks in FPGAs for particle physics

    DUARTE , J., ET AL . Fast inference of deep neural networks in FPGAs for particle physics. JINST 13, 07 (2018), P07027

    2018

  16. [24]

    Online learning for recommendations at grubhub

    EGG, A. Online learning for recommendations at grubhub. In Proceed- ings of the 15th ACM Conference on Recommender Systems(New York, NY , USA, 2021), RecSys ’21, Association for Computing Machinery, p. 569–571

    2021

  17. [25]

    FIRESTONE , D., P UTNAM , A., A NGEPAT, H., C HIOU , D., CAULFIELD , A., C HUNG , E., H UMPHREY , M., O VTCHAROV , K., P ADHYE , J., B URGER , D., M ALTZ , D., G REENBERG , A., MUNDKUR , S., D ABAGH , A., A NDREWARTHA , M., B HANU , V., CHANDRAPPA , H. K., C HATURMOHTA , S., L...

    2018

  18. [26]

    FIRESTONE , D., P UTNAM , A., M UNDKUR , S., C HIOU , D., D ABAGH , A., A NDREWARTHA , M., A NGEPAT, H., B HANU , V., CAULFIELD , A., CHUNG , E., C HANDRAPPA , H. K., C HATURMOHTA , S., H UMPHREY , M., L AVIER , J., L AM, N., L IU, F., O VTCHAROV , K., P ADHYE , J., P OPURI , ...

    2018

  19. [27]

    Tnic: A trusted nic architecture: A hardware- network substrate for building high-performance trustworthy dis- tributed systems

    GIANTSIDI , D., P RITZI , J., G UST, F., K ATSARAKIS , A., K OSHIBA , A., AND BHATOTIA , P. Tnic: A trusted nic architecture: A hardware- network substrate for building high-performance trustworthy dis- tributed systems. In Proceedings of the 30th ACM International Con- ferenc...

    2025

  20. [28]

    Fcsn: A fpga-centric smartnic frame- work for neural networks

    GUO, A., G ENG , T., Z HANG , Y., H AGHI , P., W U, C., T AN, C., L IN, Y., LI, A., AND HERBORDT , M. Fcsn: A fpga-centric smartnic frame- work for neural networks. In2022 IEEE 30th Annual International Sym- posium on Field-Programmable Custom Computing Machines (FCCM) (2022), pp. 1–2

    2022

  21. [29]

    S., M ALEVICH , A., M UDIGERE , D., S MELYANSKIY , M., X IONG , L., AND ZHANG , X

    GUPTA, U., W U, C.-J., W ANG , X., N AUMOV, M., R EAGEN , B., BROOKS , D., C OTTEL , B., H AZELWOOD , K., H EMPSTEAD , M., J IA, B., L EE, H.-H. S., M ALEVICH , A., M UDIGERE , D., S MELYANSKIY , M., X IONG , L., AND ZHANG , X. The architectural implications of facebook’s dnn-...

    2020

  22. [30]

    A., S UBRAMONI , H., C HU, C.-H., AND PANDA , D

    HAMIDOUCHE , K., V ENKATESH , A., A WAN, A. A., S UBRAMONI , H., C HU, C.-H., AND PANDA , D. K. Exploiting gpudirect rdma in designing high performance openshmem for nvidia gpu clusters. In 2015 IEEE International Conference on Cluster Computing (2015), pp. 78–87

    2015

  23. [31]

    J., R AMHORST , B., AND ALONSO , G

    HEER , M. J., R AMHORST , B., AND ALONSO , G. Machine learning- based deep packet inspection at line rate for rdma on fpgas. In Pro- ceedings of the 5th Workshop on Machine Learning and Systems (New York, NY , USA, 2025), EuroMLSys ’25, Association for Computing Machinery, p. 148–155

    2025

  24. [32]

    L., AND PATTERSON , D

    HENNESSY , J. L., AND PATTERSON , D. A. A new golden age for computer architecture. Commun. ACM 62, 2 (Jan. 2019), 48–60

    2019

  25. [33]

    S., S HANKAR , D., L U, X., WASI -U R-R AHMAN , M., AND PANDA , D

    ISLAM , N. S., S HANKAR , D., L U, X., WASI -U R-R AHMAN , M., AND PANDA , D. K. Accelerating i/o performance of big data analytics on hpc clusters through rdma-based key-value store. In 2015 44th International Conference on Parallel Processing(2015), pp. 280–289

    2015

  26. [34]

    Synchronizing disaggregated data structures with one-sided rdma: Pitfalls, experiments and design guidelines

    JASNY, M., Z IEGLER , T., N ELSON -S LIVON , J., L EIS , V., AND BIN- NIG , C. Synchronizing disaggregated data structures with one-sided rdma: Pitfalls, experiments and design guidelines. ACM Trans. Database Syst. 50, 1 (Mar. 2025)

    2025

  27. [35]

    Facl: A flexible and high-performance acl engine on fpga-based smartnic

    JIA, C., L I, C., L I, Y., H U, X., AND LI, J. Facl: A flexible and high-performance acl engine on fpga-based smartnic. In 2022 IFIP Networking Conference (IFIP Networking) (2022), pp. 1–9

    2022

  28. [36]

    Os2g: A high-performance dpu offloading architecture for gpu-based deep learning with object storage

    JIN, Z., C HEN , Y., L IANG , M., W ANG , Y., F ANG , G., Z HOU , A., ZHANG , K., X U, J., L IN, W., L IN, Y., Z HAO, S., S HI, W., H E, Z., CAI, S., AND CHEN , W. Os2g: A high-performance dpu offloading architecture for gpu-based deep learning with object storage. In Pro- cee...

    2025

  29. [37]

    KALIA , A., K AMINSKY , M., AND ANDERSEN , D. G. Using rdma efficiently for key-value services. SIGCOMM Comput. Commun. Rev. 44, 4 (Aug. 2014), 295–306

    2014

  30. [38]

    P., AND ULMER , C

    KENNY, J. P., AND ULMER , C. D. Roce: Promising technology for ethernet as a high performance networking fabric. Tech. rep., Sandia National Lab. (SNL-CA), Livermore, CA (United States), 11 2019

    2019

  31. [39]

    A survey on in-network computing: Programmable data plane and technology specific applications

    KIANPISHEH , S., AND TALEB , T. A survey on in-network computing: Programmable data plane and technology specific applications. IEEE Communications Surveys & Tutorials 25, 1 (2023), 701–761

    2023

  32. [40]

    Do OS abstractions make sense on FPGAs? In 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20) (Nov

    KOROLIJA , D., R OSCOE , T., AND ALONSO , G. Do OS abstractions make sense on FPGAs? In 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20) (Nov. 2020), USENIX Association, pp. 991–1010

    2020

  33. [41]

    PreSto: An In-Storage Data Pre- processing System for Training Recommendation Models

    LEE, Y., K IM, H., AND RHU, M. PreSto: An In-Storage Data Pre- processing System for Training Recommendation Models . In 2024 ACM/IEEE 51st Annual International Symposium on Computer Archi- tecture (ISCA) (Los Alamitos, CA, USA, July 2024), IEEE Computer Society, pp. 340–353

    2024

  34. [42]

    Compression Anal- ysis for BlueField-2/-3 Data Processing Units: Lossy and Lossless Perspectives

    LI, Y., K ASHYAP, A., G UO, Y., AND LU, X. Compression Anal- ysis for BlueField-2/-3 Data Processing Units: Lossy and Lossless Perspectives . IEEE Micro 44, 02 (Mar. 2024), 8–19

    2024

  35. [43]

    Supernic: An fpga-based, cloud-oriented smartnic

    LIN, W., SHAN , Y., KOSTA, R., K RISHNAMURTHY , A., AND ZHANG , Y. Supernic: An fpga-based, cloud-oriented smartnic. In Proceed- ings of the 2024 ACM/SIGDA International Symposium on Field Pro- grammable Gate Arrays (New York, NY , USA, 2024), FPGA ’24, As- sociation for Compu...

    2024

  36. [45]

    Honeycomb: Ordered key-value store acceleration on an fpga-based smartnic

    LIU, J., D RAGOJEVI ´C, A., F LEMING , S., K ATSARAKIS , A., K O- ROLIJA , D., Z ABLOTCHI , I., N G, H.-C., K ALIA , A., AND CASTRO , M. Honeycomb: Ordered key-value store acceleration on an fpga-based smartnic. IEEE Transactions on Computers 73, 3 (2024), 857–871

    2024

  37. [46]

    Fpga-based ai smart nics for scalable dis- tributed ai training systems

    MA, R., G EORGANAS , E., H EINECKE , A., G RIBOK , S., B OUTROS , A., AND NURVITADHI , E. Fpga-based ai smart nics for scalable dis- tributed ai training systems. IEEE Computer Architecture Letters 21, 2 (2022), 49–52

    2022

  38. [47]

    D., M IZERO , F., V EER - ARAGHAVAN , M., AND DENNIS , J

    MACARTHUR , P., L IU, Q., R USSELL , R. D., M IZERO , F., V EER - ARAGHAVAN , M., AND DENNIS , J. M. An integrated tutorial on infiniband, verbs, and mpi. IEEE Communications Surveys & Tutorials 19, 4 (2017), 2894–2926

    2017

  39. [48]

    Fpga implementation of rdma-based data acquisition system over 100-gb ethernet

    MANSOUR , W., JANVIER , N., AND FAJARDO , P. Fpga implementation of rdma-based data acquisition system over 100-gb ethernet. IEEE Transactions on Nuclear Science 66, 7 (2019), 1138–1143

    2019

  40. [49]

    Porting the roce-balboa rdma-stack from coyote to amd reconic

    MARQUART , R. Porting the roce-balboa rdma-stack from coyote to amd reconic. Master’s thesis, ETH Zurich, 2024

    2024

  41. [50]

    Microsoft azure boost, 2025

    MCINNES , M., H OLLINGSHED , M., N OTTINGHAM , C., M ALIS , S., PLANK , A., AND LEE, D. Microsoft azure boost, 2025. Accessed on April 8, 2025

    2025

  42. [51]

    Microsoft azure network adapter overview, 2025

    MCINNES , M., AND REAT, M. Microsoft azure network adapter overview, 2025. Accessed on April 8, 2025

    2025

  43. [52]

    T., D UKKIPATI , N., B LEM , E., W ASSEL , H., GHOBADI , M., V AHDAT, A., W ANG , Y., W ETHERALL , D., AND ZATS, D

    MITTAL , R., L AM, V. T., D UKKIPATI , N., B LEM , E., W ASSEL , H., GHOBADI , M., V AHDAT, A., W ANG , Y., W ETHERALL , D., AND ZATS, D. Timely: Rtt-based congestion control for the datacenter. In Proceedings of the 2015 ACM Conference on Special Interest Group on Data Commun...

    2015

  44. [53]

    fpgasys- tems/hacc: Ethz-hacc

    MOYA, J., G ABATHULER , M., R UIZ , M., AND ALONSO , G. fpgasys- tems/hacc: Ethz-hacc. Zenodo, Sept. 2023. https://doi.org/10. 5281/zenodo.8340448. 14

    2023

  45. [54]

    Jumpgate: In-Network processing as a service for data analytics

    MUSTARD , C., R UFFY, F., G AKHOKIDZE , A., B ESCHASTNIKH , I., AND FEDOROVA , A. Jumpgate: In-Network processing as a service for data analytics. In 11th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud 19) (Renton, W A, July 2019), USENIX Associ- ation

    2019

  46. [55]

    M., H UANG , J., S UNDARA - MAN , N., P ARK , J., W ANG , X., G UPTA, U., W U, C., A ZZOLINI , A

    NAUMOV, M., M UDIGERE , D., S HI, H. M., H UANG , J., S UNDARA - MAN , N., P ARK , J., W ANG , X., G UPTA, U., W U, C., A ZZOLINI , A. G., D ZHULGAKOV , D., M ALLEVICH , A., C HERNIAVSKII , I., L U, Y., KRISHNAMOORTHI , R., Y U, A., K ONDRATENKO , V., P EREIRA , S., C HEN , X....

    2019 arXiv

  47. [56]

    J., AND ALONSO , G

    RAMHORST , B., H EER , M. J., AND ALONSO , G. Coyote v2: To- wards open-source, reusable infrastructure and abstractions for fpgas. In LATTE ’25 - Workshop on Languages, Tools, and Techniques for Accelerator Design’ (2025)

    2025

  48. [57]

    Scaling up memory disaggregated applications with smart

    REN, F., Z HANG , M., C HEN , K., X IA, H., C HEN , Z., AND WU, Y. Scaling up memory disaggregated applications with smart. In Pro- ceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1 (New York, N...

    2024

  49. [58]

    ReDMArk: Bypassing RDMA security mechanisms

    ROTHENBERGER , B., T ARANOV , K., P ERRIG , A., AND HOEFLER , T. ReDMArk: Bypassing RDMA security mechanisms. In 30th USENIX Security Symposium (USENIX Security 21) (Aug. 2021), USENIX Association, pp. 4277–4292

    2021

  50. [59]

    In-network computation is a dumb idea whose time has come

    SAPIO , A., A BDELAZIZ , I., A LDILAIJAN , A., C ANINI , M., AND KAL- NIS , P. In-network computation is a dumb idea whose time has come. In Proceedings of the 16th ACM Workshop on Hot Topics in Networks (New York, NY , USA, 2017), HotNets ’17, Association for Computing Machin...

    2017

  51. [60]

    A high-throughput, resource-efficient implementa- tion of the rocev2 remote dma protocol and its application

    SCHELTEN , N., S TEINERT , F., K NAPHEIDE , J., S CHULTE , A., AND STABERNACK , B. A high-throughput, resource-efficient implementa- tion of the rocev2 remote dma protocol and its application. ACM Trans. Reconfigurable Technol. Syst. 16, 1 (Dec. 2022)

    2022

  52. [61]

    A cloud- optimized transport protocol for elastic and scalable hpc

    SHALEV , L., A YOUB , H., B SHARA , N., AND SABBAG , E. A cloud- optimized transport protocol for elastic and scalable hpc. IEEE Micro 40, 6 (2020), 67–73

    2020

  53. [62]

    Strom: smart remote memory

    SIDLER , D., WANG , Z., C HIOSA , M., K ULKARNI , A., AND ALONSO , G. Strom: smart remote memory. In Proceedings of the Fifteenth European Conference on Computer Systems (New York, NY , USA, 2020), EuroSys ’20, Association for Computing Machinery

    2020

  54. [63]

    K., S ZEKERES , A., N ELSON , J., AND ZHANG , I

    SIMPSON , A. K., S ZEKERES , A., N ELSON , J., AND ZHANG , I. Se- curing RDMA for High-Performance datacenter storage systems. In 12th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud

  55. [64]

    Edm: An ultra-low latency ethernet fabric for memory disaggregation

    SU, W., AND SHRIVASTAV, V. Edm: An ultra-low latency ethernet fabric for memory disaggregation. In Proceedings of the 30th ACM In- ternational Conference on Architectural Support for Programming Lan- guages and Operating Systems, Volume 1(New York, NY , USA, 2025), ASPLOS ’25,...

    2025

  56. [65]

    (July 2020), USENIX Association

    2020

  57. [66]

    Nevermore: Exploiting rdma mistakes in nvme- of storage applications

    TARANOV , K., R OTHENBERGER , B., D E SENSI , D., P ERRIG , A., AND HOEFLER , T. Nevermore: Exploiting rdma mistakes in nvme- of storage applications. In Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security (New York, NY , USA, 2022), CCS ’22, ...

    2022

  58. [67]

    A high-performance fpga- based roce v2 rdma packet parser and generator

    SUN, Z., G UO, Z., M A, J., AND PAN, Y. A high-performance fpga- based roce v2 rdma packet parser and generator. Electronics 13, 20 (2024)

    2024

  59. [68]

    Mellanox connectx ®-5 ex ether- net single and dual qsfp28 port adapter cards user man- ual, 2018

    TECHNOLOGIES , M. Mellanox connectx ®-5 ex ether- net single and dual qsfp28 port adapter cards user man- ual, 2018. https://gzhls.at/blob/ldb/9/a/3/2/ 073d2b59ddaec6a5a00744e21c93a3459529.pdf

    2018

  60. [69]

    sRDMA – efficient NIC-based authentication and encryption for remote direct memory access

    TARANOV , K., R OTHENBERGER , B., P ERRIG , A., AND HOEFLER , T. sRDMA – efficient NIC-based authentication and encryption for remote direct memory access. In 2020 USENIX Annual Technical Conference (USENIX ATC 20) (July 2020), USENIX Association, pp. 691–704

    2020

  61. [70]

    Designing an efficient tree index on disaggregated memory

    WANG , Q., L U, Y., AND SHU, J. Designing an efficient tree index on disaggregated memory. Commun. ACM (Apr. 2025). Online First

    2025

  62. [71]

    A case for RDMA in clouds: turning supercomputer networking into commodity

    TRIVEDI , A., M ETZLER , B., AND STUEDI , P. A case for RDMA in clouds: turning supercomputer networking into commodity. In APSys ’11 Asia Pacific Workshop on Systems, Shanghai, China, July 11-12, 2011 (2011), H. Chen, Z. Zhang, S. Moon, and Y . Zhou, Eds., ACM, p. 17

    2011

  63. [72]

    Xilinx embedded target rdma enabled nic v1.1, 2018

    XILINX . Xilinx embedded target rdma enabled nic v1.1, 2018. https: //docs.amd.com/v/u/en-US/pg294-etrnic

    2018

  64. [73]

    Fp- gaNIC: An FPGA-based versatile 100gb SmartNIC for GPUs

    WANG , Z., H UANG , H., Z HANG , J., W U, F., AND ALONSO , G. Fp- gaNIC: An FPGA-based versatile 100gb SmartNIC for GPUs. In 2022 USENIX Annual Technical Conference (USENIX ATC 22)(Carlsbad, CA, July 2022), USENIX Association, pp. 967–986

    2022

  65. [74]

    FORD: Fast one- sided RDMA-based distributed transactions for disaggregated persistent memory

    ZHANG , M., H UA, Y., Z UO, P., AND LIU, L. FORD: Fast one- sided RDMA-based distributed transactions for disaggregated persistent memory. In 20th USENIX Conference on File and Storage Technolo- gies (FAST 22) (Santa Clara, CA, Feb. 2022), USENIX Association, pp. 51–68

    2022

  66. [75]

    Prop: Using pcie-based rdma to accelerate rack-scale communications in data centers

    ZANG , D., C AO, Z., L IU, X., W ANG , L., W ANG , Z., AND SUN, N. Prop: Using pcie-based rdma to accelerate rack-scale communications in data centers. In 2015 IEEE 21st International Conference on Parallel and Distributed Systems (ICPADS) (2015), pp. 465–472

    2015

  67. [76]

    Goldminer: Elastic scaling of training data pre-processing pipelines for deep learning

    ZHAO, H., Y ANG , Z., C HENG , Y., T IAN , C., R EN, S., X IAO, W., YUAN, M., C HEN , L., L IU, K., Z HANG , Y., L I, Y., AND LIN, W. Goldminer: Elastic scaling of training data pre-processing pipelines for deep learning. Proc. ACM Manag. Data 1, 2 (June 2023)

    2023

  68. [77]

    Is network the bottleneck of distributed training? In Proceedings of the 2020 Workshop on Network Meets AI & ML, NetAI@SIGCOMM, Virtual Event, USA, August 14, 2020(2020), B

    ZHANG , Z., C HANG , C., L IN, H., W ANG , Y., A RORA , R., AND JIN, X. Is network the bottleneck of distributed training? In Proceedings of the 2020 Workshop on Network Meets AI & ML, NetAI@SIGCOMM, Virtual Event, USA, August 14, 2020(2020), B. Arzani and X. Jin, Eds., ACM, pp. 8–13

    2020

  69. [78]

    Understanding data storage and ingestion for large- scale deep recommendation model training: industrial product

    ZHAO, M., AGARWAL , N., BASANT , A., G EDIK , B., PAN, S., O ZDAL , M., K OMURAVELLI , R., P AN, J., B AO, T., L U, H., N ARAYANAN , S., LANGMAN , J., WILFONG , K., RASTOGI , H., WU, C.-J., K OZYRAKIS , C., AND POL, P. Understanding data storage and ingestion for large- scale ...

    2022

  70. [80]

    A primer on reconic: Rdma-enabled compute offloading on smartnic, 2023

    ZHONG , G., K OLEKAR , A., A MORNPAISANNON , B., C HOI , I., JAVAID, H., AND BALDI , M. A primer on reconic: Rdma-enabled compute offloading on smartnic, 2023

    2023

  71. [81]

    Embedding in recommender systems: A survey

    ZHAO, X., W ANG , M., Z HAO, X., L I, J., Z HOU , S., Y IN, D., L I, Q., T ANG , J., AND GUO, R. Embedding in recommender systems: A survey. arXiv preprint in arXiv:2310.18608 (2023)

    2023

  72. [82]

    Efficient tabular data prepro- cessing of ml pipelines

    ZHU, Y., J IANG , W., AND ALONSO , G. Efficient tabular data prepro- cessing of ml pipelines. arXiv preprint arXiv:2409.14912 (2024)

    2024 arXiv

  73. [83]

    H., AND ZHANG , M

    ZHU, Y., E RAN , H., F IRESTONE , D., G UO, C., L IPSHTEYN , M., LIRON , Y., PADHYE , J., R AINDEL , S., Y AHIA , M. H., AND ZHANG , M. Congestion control for large-scale rdma deployments. In Pro- ceedings of the 2015 ACM Conference on Special Interest Group on Data Communicat...

    2015

  74. [84]

    Race: One-sided rdma-conscious extendible hashing

    ZUO, P., ZHOU , Q., SUN, J., YANG , L., ZHANG , S., HUA, Y., CHENG , J., H E, R., AND YAN, H. Race: One-sided rdma-conscious extendible hashing. ACM Trans. Storage 18, 2 (Apr. 2022). 16

    2022

  75. [85]

    One-sided RDMA-Conscious extendible hashing for disaggregated memory

    ZUO, P., S UN, J., Y ANG , L., Z HANG , S., AND HUA, Y. One-sided RDMA-Conscious extendible hashing for disaggregated memory. In 2021 USENIX Annual Technical Conference (USENIX ATC 21)(July 2021), USENIX Association, pp. 15–29

    2021

  76. [2024]

    https://docs.amd.com/r/en-US/pg195-pcie-dma

Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.