pith. sign in

arxiv: 2508.03515 · v2 · submitted 2025-08-05 · ❄️ cond-mat.dis-nn · cond-mat.mtrl-sci

Oxide Interface-Based Polymorphic Electronic Devices for Neuromorphic Computing

Soumen Pradhan (1) , Kirill Miller (1) , Fabian Hartmann (1) , Merit Spring (2) , Judith Gabel (2) , Berengar Leikert (2) , Silke Kuhn (1) , Martin Kamp (1)
show 13 more authors
Victor Lopez-Richard (3) Michael Sing (2) Ralph Claessen (2) Sven H\"ofling (1) ((1) Julius-Maximilians-Universit\"at W\"urzburg Physikalisches Institut W\"urzburg-Dresden Cluster of Excellence ct.qmat Lehrstuhl f\"urTechnische Physik Germany (2) Julius-Maximilians-Universit\"at W\"urzburg Experimentelle Physik 4 (3) Universidade Federal de S\~ao Carlos Departamento de F\'isica Brazil)
This is my paper

Pith reviewed 2026-05-19 00:15 UTC · model grok-4.3

classification ❄️ cond-mat.dis-nn cond-mat.mtrl-sci
keywords oxide interfacesLaAlO3/SrTiO3polymorphic devicesneuromorphic computingmemristormemcapacitorreservoir computingsynaptic plasticity
0
0 comments X

The pith

Lateral gates program a single LaAlO3/SrTiO3 interface device to act as a transistor, memristor or memcapacitor.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows how voltages applied to lateral gates can reconfigure the electron gas at an oxide interface to produce three distinct electronic behaviors in the same device. One circuit built from these modes performs reservoir computing through its nonlinear response and short-term memory. Another circuit uses the same hardware to shift between short-term and long-term synaptic responses while storing logic outputs in place. A reader cares because the work points to hardware that merges processing and memory without the usual separation of units, potentially cutting energy use in AI systems while remaining compatible with silicon fabrication.

Core claim

By manipulating the quasi-two-dimensional electron gas in LaAlO3/SrTiO3 heterostructures using lateral gates, we demonstrate oxide-interface based polymorphic electronic devices with programmable transistor, memristor, and memcapacitor functionalities. A circuit utilizing transistor and memcapacitor modes exhibits nonlinearity and short-term memory for physical reservoir computing. An integrated circuit with transistor and memristor modes enables the transition from short- to long-term synaptic plasticity, logic operations, and in-situ logic output storage, supporting reconfigurable synaptic logic for multi-input decision-making tasks such as patient-monitoring.

What carries the argument

The quasi-two-dimensional electron gas at the LaAlO3/SrTiO3 interface, tuned by lateral gates to produce distinct and switchable transistor, memristor, or memcapacitor responses.

If this is right

  • Circuits combining transistor and memcapacitor modes implement physical reservoir computing through built-in nonlinearity and short-term memory.
  • Transistor and memristor modes together allow controlled shifts from short-term to long-term synaptic plasticity with in-place logic storage.
  • Reconfigurable synaptic logic on the same platform supports multi-input decision tasks such as healthcare monitoring.
  • The approach enables monolithic oxide integrated circuits that remain silicon-compatible and energy-efficient.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The single-device polymorphism could reduce the total number of distinct components required in neuromorphic circuits.
  • Integration with conventional silicon processes might allow hybrid chips that combine oxide interfaces with standard CMOS logic.
  • Energy savings would follow if the merged computation-and-memory operation avoids the data movement overhead of separate memory units.
  • Stability tests on larger arrays of these devices would show whether gate crosstalk scales acceptably for practical circuit sizes.

Load-bearing premise

The interface electron gas can be driven by lateral gates into separate, stable, and repeatable transistor, memristor, and memcapacitor states without crosstalk or rapid degradation.

What would settle it

Repeated cycling between the three modes on the same device produces drifting thresholds, loss of distinct behaviors, or measurable crosstalk between gates after a few hundred operations.

read the original abstract

Aside from recent advances in artificial intelligence (AI) models, specialized AI hardware is crucial to address large volumes of unstructured and dynamic data. Hardware-based AI, built on conventional complementary metal-oxidesemiconductor (CMOS)-technology, faces several critical challenges including scaling limitation of devices [1, 2], separation of computation and memory units [3] and most importantly, overall system energy efficiency [4]. While numerous materials with emergent functionalities have been proposed to overcome these limitations, scalability, reproducibility, and compatibility remain critical obstacles [5, 6]. Here, we demonstrate oxide-interface based polymorphic electronic devices with programmable transistor, memristor, and memcapacitor functionalities by manipulating the quasi-two-dimensional electron gas in LaAlO3/SrTiO3 heterostructures [7, 8] using lateral gates. A circuit utilizing two polymorphic functionalities of transistor and memcapacitor exhibits nonlinearity and short-term memory, enabling implementation in physical reservoir computing. An integrated circuit incorporating transistor and memristor functionalities is utilized for the transition from short- to long-term synaptic plasticity and for logic operations, along with in-situ logic output storage. The same circuit with advanced reconfigurable synaptic logic operations presents high-level multi-input decision-making tasks, such as patient-monitoring in healthcare applications. Our findings pave the way for oxide-based monolithic integrated circuits in a scalable, silicon compatible, energy efficient single platform, advancing both the polymorphic and neuromorphic computings.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript demonstrates polymorphic electronic devices based on LaAlO3/SrTiO3 heterostructures, where lateral gates manipulate the quasi-two-dimensional electron gas to program transistor, memristor, and memcapacitor functionalities in the same channel. It further reports circuit-level demonstrations using combinations of these modes for physical reservoir computing with nonlinearity and short-term memory, transition from short- to long-term synaptic plasticity with logic operations and in-situ storage, and reconfigurable multi-input decision-making tasks such as healthcare monitoring.

Significance. If the central experimental claims hold with adequate supporting data, the work would be significant for neuromorphic hardware by showing a silicon-compatible, monolithic platform that integrates multiple reconfigurable functionalities without separate device types, potentially addressing energy efficiency and integration challenges in AI accelerators. The polymorphic approach via oxide interfaces is a clear strength if reproducibility is established.

major comments (2)
  1. [Device characterization and programming results] The load-bearing claim that lateral gates produce three distinct, stable, and reproducible functionalities (transistor, memristor, memcapacitor) without crosstalk or degradation requires quantitative evidence; the manuscript should report gate-to-gate isolation metrics, retention times under repeated cycling, and device-to-device statistics in the device characterization results.
  2. [Circuit-level implementations and applications] For the circuit demonstrations of reservoir computing and synaptic logic, performance metrics such as energy per operation, endurance under cycling, and comparison to baseline CMOS or other neuromorphic implementations are needed to support the claimed advantages in energy efficiency and scalability.
minor comments (2)
  1. [Abstract] The abstract contains a typographical error: 'complementary metal-oxidesemiconductor' should read 'complementary metal-oxide-semiconductor'.
  2. [Figures] Figure captions and axis labels should explicitly state measurement conditions (e.g., temperature, sweep rates) to aid reproducibility.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We are grateful to the referee for their positive evaluation of the significance of our work and for the detailed comments that help improve the manuscript. Below we provide point-by-point responses to the major comments.

read point-by-point responses

  1. Referee: [Device characterization and programming results] The load-bearing claim that lateral gates produce three distinct, stable, and reproducible functionalities (transistor, memristor, memcapacitor) without crosstalk or degradation requires quantitative evidence; the manuscript should report gate-to-gate isolation metrics, retention times under repeated cycling, and device-to-device statistics in the device characterization results.

    Authors: We thank the referee for this important comment. While the original manuscript includes cycling stability and retention data in the supplementary information, we agree that additional quantitative metrics would strengthen the presentation. In the revised manuscript we have added explicit gate-to-gate isolation metrics, extended retention times under repeated cycling, and device-to-device statistics from multiple fabricated devices. These updates appear in the revised device characterization section, an updated Figure 2, and new supplementary figures. revision: yes

  2. Referee: [Circuit-level implementations and applications] For the circuit demonstrations of reservoir computing and synaptic logic, performance metrics such as energy per operation, endurance under cycling, and comparison to baseline CMOS or other neuromorphic implementations are needed to support the claimed advantages in energy efficiency and scalability.

    Authors: We agree that these metrics provide useful context for the claimed advantages. In the revised manuscript we have added energy-per-operation estimates derived from the measured device currents and voltages, endurance data for the circuit demonstrations under extended cycling, and a comparative discussion with CMOS and other neuromorphic platforms in the discussion section. revision: yes

Circularity Check

0 steps flagged

Experimental demonstration with no derivation chain or fitted predictions

full rationale

The paper reports fabrication and electrical characterization of LaAlO3/SrTiO3 devices that exhibit programmable transistor, memristor, and memcapacitor modes under lateral gating. No equations, ansatzes, uniqueness theorems, or parameter-fitting steps appear in the provided text. The central claims rest on measured I-V curves, retention data, and circuit-level demonstrations rather than any reduction of a 'prediction' to its own inputs. Self-citations are absent from the load-bearing steps; cited references [7,8] are the foundational LAO/STO interface literature. The work is therefore self-contained against external experimental benchmarks and carries no circularity burden.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The demonstration rests on established properties of LaAlO3/SrTiO3 interfaces rather than new postulates or fitted parameters.

axioms (1)
  • domain assumption Quasi-two-dimensional electron gas forms at the LaAlO3/SrTiO3 interface and can be modulated by lateral electrostatic gates
    Invoked in the abstract as the basis for achieving polymorphic functionalities.

pith-pipeline@v0.9.0 · 5948 in / 1224 out tokens · 42915 ms · 2026-05-19T00:15:14.326827+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Gate-controlled analog memcapacitance in LaAlO3/SrTiO3 interface-based devices

    physics.app-ph 2025-12 unverdicted novelty 4.0

    Gate-tunable analog memcapacitance is demonstrated in LaAlO3/SrTiO3 interface devices, originating from lateral floating gate charge localization with a supporting model.

Reference graph

Works this paper leans on

59 extracted references · 59 canonical work pages · cited by 1 Pith paper

  1. [1]

    Computer 48(12), 14–23 (2015)

    Shalf, J.M., Leland, R.: Computing beyond Moore’s law. Computer 48(12), 14–23 (2015)

    work page 2015

  2. [2]

    Nanobiotechnology Reports 17(1), 24–38 (2022)

    Bespalov, V., Dyuzhev, N., Kireev, V.Y.: Possibilities and limitations of CMOS Technology for the production of various Microelectronic systems and devices. Nanobiotechnology Reports 17(1), 24–38 (2022)

    work page 2022

  3. [3]

    : Bridging biological and artificial neural networks with emerg- ing neuromorphic devices: fundamentals, progress, and challenges

    Tang, J., Yuan, F., Shen, X., Wang, Z., Rao, M., He, Y., Sun, Y., Li, X., Zhang, 13 W., Li, Y., et al. : Bridging biological and artificial neural networks with emerg- ing neuromorphic devices: fundamentals, progress, and challenges. Adv. Mater. 31(49), 1902761 (2019)

    work page 2019

  4. [4]

    AI hardware has an energy problem. Nat. Electron. 6(7), 463–463 (2023) https: //doi.org/10.1038/s41928-023-01014-x

    work page doi:10.1038/s41928-023-01014-x 2023

  5. [5]

    Singh, D.K., Gupta, G.: Brain-inspired computing: can 2D materials bridge the gap between biological and artificial neural networks? Mater. Adv. 5(8), 3158– 3172 (2024)

    work page 2024

  6. [6]

    Neuromorphic Computing and Engineering 2(3), 032004 (2022)

    Zhang, Z., Yang, D., Li, H., Li, C., Wang, Z., Sun, L., Yang, H.: 2D materials and van der Waals heterojunctions for neuromorphic computing. Neuromorphic Computing and Engineering 2(3), 032004 (2022)

    work page 2022

  7. [7]

    Nature 427(6973), 423–426 (2004)

    Ohtomo, A., Hwang, H.: A high-mobility electron gas at the LaAlO 3/SrTiO3 heterointerface. Nature 427(6973), 423–426 (2004)

    work page 2004

  8. [8]

    Science 313(5795), 1942–1945 (2006)

    Thiel, S., Hammerl, G., Schmehl, A., Schneider, C.W., Mannhart, J.: Tun- able quasi-two-dimensional electron gases in oxide heterostructures. Science 313(5795), 1942–1945 (2006)

    work page 1942

  9. [9]

    Nature 561(7722), 163–166 (2018)

    Jones, N.: How to stop data centres from gobbling up the world’s electricity. Nature 561(7722), 163–166 (2018)

    work page 2018

  10. [10]

    Nature 626, 693 (2024)

    Crawford, K.: Generative AI’s environmental costs are soaring-and mostly secret. Nature 626, 693 (2024)

    work page 2024

  11. [11]

    In: 2022 International Joint Conference on Neural Networks (IJCNN), pp

    Sevilla, J., Heim, L., Ho, A., Besiroglu, T., Hobbhahn, M., Villalobos, P.: Com- pute trends across three eras of machine learning. In: 2022 International Joint Conference on Neural Networks (IJCNN), pp. 1–8 (2022). IEEE

    work page 2022

  12. [12]

    Circuits and Systems 2(4), 358–364 (2011)

    Hentrich, D., Oruklu, E., Saniie, J.: Polymorphic computing: definition, trends, and a new agent-based architecture. Circuits and Systems 2(4), 358–364 (2011)

    work page 2011

  13. [13]

    In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp

    Raitza, M., Kumar, A., V¨ olp, M., Walter, D., Trommer, J., Mikolajick, T., Weber, W.M.: Exploiting transistor-level reconfiguration to optimize combinational cir- cuits. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp. 338–343 (2017). IEEE

    work page 2017

  14. [14]

    Yang, R., Huang, H.-M., Guo, X.: Memristive synapses and neurons for bioin- spired computing. Adv. Electron. Mater. 5(9), 1900287 (2019)

    work page 2019

  15. [15]

    Danial, L., Pikhay, E., Herbelin, E., Wainstein, N., Gupta, V., Wald, N., Roizin, Y., Daniel, R., Kvatinsky, S.: Two-terminal floating-gate transistors with a low- power memristive operation mode for analogue neuromorphic computing. Nat. Electron. 2(12), 596–605 (2019) 14

    work page 2019

  16. [16]

    Du, C., Cai, F., Zidan, M.A., Ma, W., Lee, S.H., Lu, W.D.: Reservoir computing using dynamic memristors for temporal information processing. Nat. Commun. 8(1), 2204 (2017)

    work page 2017

  17. [17]

    : Designing a bidirec- tional, adaptive neural interface incorporating machine learning capabilities and memristor-enhanced hardware

    Shchanikov, S., Zuev, A., Bordanov, I., Danilin, S., Lukoyanov, V., Korolev, D., Belov, A., Pigareva, Y., Gladkov, A., Pimashkin, A., et al. : Designing a bidirec- tional, adaptive neural interface incorporating machine learning capabilities and memristor-enhanced hardware. Chaos, solitons & fractals 142, 110504 (2021)

    work page 2021

  18. [18]

    Wang, Y., Sun, Q., Yu, J., Xu, N., Wei, Y., Cho, J.H., Wang, Z.L.: Boolean logic computing based on neuromorphic transistor. Adv. Funct. Mater. 33(47), 2305791 (2023)

    work page 2023

  19. [19]

    IEEE Transactions on Computers 100(1), 73–78 (1970)

    Stone, H.S.: A logic-in-memory computer. IEEE Transactions on Computers 100(1), 73–78 (1970)

    work page 1970

  20. [20]

    Choi, Y., Ho, D.H., Kim, S., Choi, Y.J., Roe, D.G., Kwak, I.C., Min, J., Han, H., Gao, W., Cho, J.H.: Physically defined long-term and short-term synapses for the development of reconfigurable analog-type operators capable of performing health care tasks. Sci. Adv. 9(27), 5946 (2023)

    work page 2023

  21. [21]

    : Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing

    Fuller, E.J., Keene, S.T., Melianas, A., Wang, Z., Agarwal, S., Li, Y., Tuchman, Y., James, C.D., Marinella, M.J., Yang, J.J., et al. : Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing. Science 364(6440), 570–574 (2019)

    work page 2019

  22. [22]

    : CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

    Chen, W.-H., Dou, C., Li, K.-X., Lin, W.-Y., Li, P.-Y., Huang, J.-H., Wang, J.- H., Wei, W.-C., Xue, C.-X., Chiu, Y.-C., et al. : CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors. Nat. Electron. 2(9), 420–428 (2019)

    work page 2019

  23. [23]

    Cao, G., Meng, P., Chen, J., Liu, H., Bian, R., Zhu, C., Liu, F., Liu, Z.: 2d material based synaptic devices for neuromorphic computing. Adv. Funct. Mater. 31(4), 2005443 (2021)

    work page 2021

  24. [24]

    Liu, C., Chen, H., Wang, S., Liu, Q., Jiang, Y.-G., Zhang, D.W., Liu, M., Zhou, P.: Two-dimensional materials for next-generation computing technologies. Nat. Nanotechnol. 15(7), 545–557 (2020)

    work page 2020

  25. [25]

    : Zero-power optoelectronic synaptic devices

    Huang, W., Hang, P., Wang, Y., Wang, K., Han, S., Chen, Z., Peng, W., Zhu, Y., Xu, M., Zhang, Y., et al. : Zero-power optoelectronic synaptic devices. Nano Energy 73, 104790 (2020)

    work page 2020

  26. [26]

    ACS Appl

    Dai, S., Wu, X., Liu, D., Chu, Y., Wang, K., Yang, B., Huang, J.: Light-stimulated synaptic devices utilizing interfacial effect of organic field-effect transistors. ACS Appl. Mater. Interfaces. 10(25), 21472–21480 (2018) 15

    work page 2018

  27. [27]

    Nano Energy 62, 393–400 (2019)

    Chen, Y., Qiu, W., Wang, X., Liu, W., Wang, J., Dai, G., Yuan, Y., Gao, Y., Sun, J.: Solar-blind SnO 2 nanowire photo-synapses for associative learning and coincidence detection. Nano Energy 62, 393–400 (2019)

    work page 2019

  28. [28]

    Goswami, P., Vashishtha, P., Yadav, A., Prajapat, P., Goswami, L., Gupta, G.: Fabrication of highly sensitive visible photodetector based on SnS 2 terrazzo-like structure for weak signal detection. Opt. Mater. 145, 114406 (2023)

    work page 2023

  29. [29]

    Singh, D.K., Pant, R.K., Nanda, K.K., Krupanidhi, S.B.: Pulsed laser deposition for conformal growth of MoS 2 on gan nanorods for highly efficient self-powered photodetection. Mater. Adv. 3(15), 6343–6351 (2022)

    work page 2022

  30. [30]

    Tang, H., Neupane, B., Neupane, S., Ruan, S., Nepal, N.K., Ruzsinszky, A.: Tun- able band gaps and optical absorption properties of bent MoS 2 nanoribbons. Sci. Rep. 12(1), 3008 (2022)

    work page 2022

  31. [31]

    : Programmable graded doping for reconfigurable molybdenum ditelluride devices

    Peng, R., Wu, Y., Wang, B., Shi, R., Xu, L., Pan, T., Guo, J., Zhao, B., Song, C., Fan, Z., et al. : Programmable graded doping for reconfigurable molybdenum ditelluride devices. Nat. Electron. 6(11), 852–861 (2023)

    work page 2023

  32. [32]

    Tsai, M.-Y., Huang, C.-T., Lin, C.-Y., Lee, M.-P., Yang, F.-S., Li, M., Chang, Y.- M., Watanabe, K., Taniguchi, T., Ho, C.-H.,et al.: A reconfigurable transistor and memory based on a two-dimensional heterostructure and photoinduced trapping. Nat. Electron. 6(10), 755–764 (2023)

    work page 2023

  33. [33]

    Solid-State Electronics102, 12–24 (2014)

    Weber, W., Heinzig, A., Trommer, J., Martin, D., Grube, M., Mikolajick, T.: Reconfigurable nanowire electronics - a review. Solid-State Electronics102, 12–24 (2014)

    work page 2014

  34. [34]

    : Efficient data processing using tunable entropy- stabilized oxide memristors

    Yoo, S., Chae, S., Chiang, T., Webb, M., Ma, T., Paik, H., Park, Y., Williams, L., Nomoto, K., Xing, H.G., et al. : Efficient data processing using tunable entropy- stabilized oxide memristors. Nat. Electron. 7(6), 466–474 (2024)

    work page 2024

  35. [35]

    : Thousands of conductance levels in memristors integrated on CMOS

    Rao, M., Tang, H., Wu, J., Song, W., Zhang, M., Yin, W., Zhuo, Y., Kiani, F., Chen, B., Jiang, X., et al. : Thousands of conductance levels in memristors integrated on CMOS. Nature 615(7954), 823–829 (2023)

    work page 2023

  36. [36]

    Demasius, K.-U., Kirschen, A., Parkin, S.: Energy-efficient memcapacitor devices for neuromorphic computing. Nat. Electron. 4(10), 748–756 (2021)

    work page 2021

  37. [37]

    MRS Bull

    Mannhart, J., Blank, D.H., Hwang, H., Millis, A., Triscone, J.-M.: Two- dimensional electron gases at oxide interfaces. MRS Bull. 33(11), 1027–1034 (2008)

    work page 2008

  38. [38]

    Bi, F., Huang, M., Bark, C.-W., Ryu, S., Lee, S., Eom, C.-B., Irvin, P., Levy, J.: Electro-mechanical response of top-gated LaAlO3/SrTiO3. J. Appl. Phys. 119(2) (2016) 16

    work page 2016

  39. [39]

    Nano Lett

    Goswami, S., Mulazimoglu, E., Vandersypen, L.M., Caviglia, A.D.: Nanoscale electrostatic control of oxide interfaces. Nano Lett. 15(4), 2627–2632 (2015)

    work page 2015

  40. [40]

    experiments, methods, and perspectives

    Giampietri, A., Drera, G., Sangaletti, L.: Band alignment at heteroepitaxial per- ovskite oxide interfaces. experiments, methods, and perspectives. Adv. Mater. Interfaces 4(11), 1700144 (2017)

    work page 2017

  41. [41]

    : Gate-tunable giant nonreciprocal charge transport in noncentrosymmetric oxide interfaces

    Choe, D., Jin, M.-J., Kim, S.-I., Choi, H.-J., Jo, J., Oh, I., Park, J., Jin, H., Koo, H.C., Min, B.-C., et al. : Gate-tunable giant nonreciprocal charge transport in noncentrosymmetric oxide interfaces. Nat. Commun. 10(1), 4510 (2019)

    work page 2019

  42. [42]

    Schneider, C.W., Thiel, S., Hammerl, G., Richter, C., Mannhart, J.: Microlithog- raphy of electron gases formed at interfaces in oxide heterostructures. Appl. Phys. Lett. 89(12) (2006)

    work page 2006

  43. [43]

    Miller, K., Hartmann, F., Leikert, B., Kuhn, S., Gabel, J., Sing, M., Claessen, R., H¨ ofling, S.: Room temperature memristive switching in nano-patterned LaAlO3/SrTiO3 wires with laterally defined gates. Appl. Phys. Lett. 118(15) (2021)

    work page 2021

  44. [44]

    Nano Lett

    Monteiro, A., Groenendijk, D., Manca, N., Mulazimoglu, E., Goswami, S., Blanter, Y., Vandersypen, L., Caviglia, A.: Side gate tunable Josephson junctions at the LaAlO 3/SrTiO3 interface. Nano Lett. 17(2), 715–720 (2017)

    work page 2017

  45. [45]

    Stornaiuolo, D., Gariglio, S., Fˆ ete, A., Gabay, M., Li, D., Massarotti, D., Triscone, J.-M.: Weak localization and spin-orbit interaction in side-gate field effect devices at the LaAlO 3/SrTiO3 interface. Phys. Rev. B 90(23), 235426 (2014)

    work page 2014

  46. [46]

    Maier, P., Hartmann, F., Gabel, J., Frank, M., Kuhn, S., Scheiderer, P., Leik- ert, B., Sing, M., Worschech, L., Claessen, R., et al.: Gate-tunable, normally-on to normally-off memristance transition in patterned LaAlO 3/SrTiO3 interfaces. Appl. Phys. Lett. 110(9) (2017)

    work page 2017

  47. [47]

    Proceedings of the IEEE 97(10), 1717–1724 (2009)

    Di Ventra, M., Pershin, Y.V., Chua, L.O.: Circuit elements with memory: Mem- ristors, memcapacitors, and meminductors. Proceedings of the IEEE 97(10), 1717–1724 (2009)

    work page 2009

  48. [48]

    NPG Asia Mater

    Wu, S., Wu, G., Qing, J., Zhou, X., Bao, D., Yang, G., Li, S.: Electrically induced colossal capacitance enhancement in LaAlO3/SrTiO3 heterostructures. NPG Asia Mater. 5(10), 65–65 (2013)

    work page 2013

  49. [49]

    Kim, S.K., Kim, S.-I., Lim, H., Jeong, D.S., Kwon, B., Baek, S.-H., Kim, J.-S.: Electric-field-induced shift in the threshold voltage in LaAlO 3/SrTiO3 heterostructures. Sci. Rep. 5(1), 8023 (2015)

    work page 2015

  50. [50]

    IEEE Trans

    Silva, R.S.W., Hartmann, F., Lopez-Richard, V.: The ubiquitous memristive response in solids. IEEE Trans. Electron Devices 69(9), 5351–5356 (2022) 17

    work page 2022

  51. [51]

    Science 332(6031), 825–828 (2011)

    Li, L., Richter, C., Paetel, S., Kopp, T., Mannhart, J., Ashoori, R.: Very large capacitance enhancement in a two-dimensional electron system. Science 332(6031), 825–828 (2011)

    work page 2011

  52. [52]

    Pei, M., Zhu, Y., Liu, S., Cui, H., Li, Y., Yan, Y., Li, Y., Wan, C., Wan, Q.: Power-efficient multisensory reservoir computing based on Zr-doped HfO 2 memcapacitive synapse arrays. Adv. Mater. 35(41), 2305609 (2023)

    work page 2023

  53. [53]

    Bayat, F.M., Prezioso, M., Chakrabarti, B., Nili, H., Kataeva, I., Strukov, D.: Implementation of multilayer perceptron network with highly uniform passive memristive crossbar circuits. Nat. Commun. 9(1), 2331 (2018)

    work page 2018

  54. [54]

    Nature 565(7737), 35–42 (2019)

    Manipatruni, S., Nikonov, D.E., Lin, C.-C., Gosavi, T.A., Liu, H., Prasad, B., Huang, Y.-L., Bonturim, E., Ramesh, R., Young, I.A.: Scalable energy-efficient magnetoelectric spin-orbit logic. Nature 565(7737), 35–42 (2019)

    work page 2019

  55. [55]

    : Superconducting interfaces between insulating oxides

    Reyren, N., Thiel, S., Caviglia, A., Kourkoutis, L.F., Hammerl, G., Richter, C., Schneider, C.W., Kopp, T., Ruetschi, A.-S., Jaccard, D., et al. : Superconducting interfaces between insulating oxides. Science 317(5842), 1196–1199 (2007)

    work page 2007

  56. [56]

    Li, L., Richter, C., Mannhart, J., Ashoori, R.C.: Coexistence of magnetic order and two-dimensional superconductivity at LaAlO3/SrTiO3 interfaces. Nat. Phys. 7(10), 762–766 (2011)

    work page 2011

  57. [57]

    0” and “1

    Qian, C., Kong, L.-a., Yang, J., Gao, Y., Sun, J.: Multi-gate organic neuron transistors for spatiotemporal information processing. Appl. Phys. Lett. 110(8) (2017) Methods Device fabrication The devices were fabricated in main three steps. In the first step, a TiO 2 terminated (001)-oriented STO substrate was spin-coated with negative photoresist. Then th...

    work page 2017

  58. [58]

    The ubiquitous memristive response in solids

    Silva, Rafael Schio Wengenroth, Fabian Hartmann, and Victor Lopez -Richard. "The ubiquitous memristive response in solids." IEEE Transactions on Electron Devices 69.9 (2022): 5351-5356

    work page 2022

  59. [59]

    A logic‐memory transistor with the integration of visible information sensing‐memory‐processing

    Hou, Xiang, et al. "A logic‐memory transistor with the integration of visible information sensing‐memory‐processing." Advanced Science 7.21 (2020): 2002072. Figure S10: Logic AND operation in 2T1M device: a, schematic diagram of 2T1M circuit diagram where two transistors and one memristor are connected in series, and corresponding b, output current (Iout)...

    work page 2020