Fast entangling gates on fluxoniums via parametric modulation of plasmon interaction
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In superconducting quantum processors, exploring diverse control methods could offer essential versatility and redundancy to mitigate challenges such as frequency crowding, spurious couplings, control crosstalk, and fabrication variability, thus leading to better system-level performance. Here we introduce a control strategy for fast entangling gates in a scalable fluxonium architecture, utilizing parametric modulation of the plasmon interaction. In this architecture, fluxoniums are coupled via a tunable coupler, whose transition frequency is flux-modulated to control the inter-fluxonium plasmon interaction. A bSWAP-type interaction is activated by parametrically driving the coupler at the sum frequency of the plasmon transitions of the two fluxoniums, resulting in the simultaneous excitation or de-excitation of both plasmon modes. This strategy therefore allow the transitions between computational states and non-computational plasmon states, enabling the accumulation of conditional phases on the computational subspace and facilitating the realization of controlled-phase gates. By focusing on a specific case of these bSWAP-type interactions, we show that a simple drive pulse enables sub-100ns CZ gates with an error below $10^{-4}$. Given its operational flexibility and extensibility, this approach could potentially offer a foundational framework for developing scalable fluxonium-based quantum processors.
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Cited by 2 Pith papers
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Extensible Fluxonium Architecture Using Tunable Couplers with Low Shunt Capacitance
The paper introduces an extensible 2D fluxonium qubit architecture using low-shunt-capacitance tunable couplers realized as quarton or fluxonium circuits to enable strong tunable interactions and multiple connections ...
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Long-range tunable coupler for modular fluxonium quantum processors
A tunable coupler design enables sub-100 ns two-qubit gates with errors below 10^{-4} between fluxonium qubits over 1 cm distances for modular architectures.
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