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arxiv: 2601.22804 · v2 · submitted 2026-01-30 · 💻 cs.CR · cs.AR

Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms

Rourab Paul , Krishnendu Guha , Amlan Chakrabarti This is my paper

Pith reviewed 2026-05-16 09:31 UTC · model grok-4.3

classification 💻 cs.CR cs.AR
keywords Number Theoretic TransformHardware TrojansPost-Quantum CryptographyFault DetectionControl FlowFPGA ImplementationKyber
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The pith

A modified Number Theoretic Transform detects and corrects control-flow disruptions and timing faults from hardware Trojans in post-quantum cryptography.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a secure NTT design for lattice-based algorithms such as Kyber that adds detection for unconventional delays and control-flow changes. These faults can be caused by hardware Trojans inserted on control signals, which are low-cost yet capable of bypassing entire computation sequences or enabling side-channel attacks. The architecture includes adaptive correction modules that respond to detected issues. Implementation results on Artix-7 FPGA show high fault detection and correction success rates across Kyber variants. The added modules produce only modest increases in area and execution time.

Core claim

The secure NTT architecture detects unconventional delays, control-flow disruptions, and soft analytical side-channel attacks induced by hardware Trojans on control signals, then applies adaptive fault correction to mitigate them, achieving high success rates in simulation and FPGA tests while keeping area and time overheads modest.

What carries the argument

Fault detection and adaptive correction modules integrated into the NTT pipeline that monitor control signals for disruptions and timing anomalies.

If this is right

  • PQC implementations on reconfigurable hardware can resist both accidental faults and intentional Trojan attacks on control paths.
  • The same detection approach applies across different Kyber parameter sets without major redesign.
  • Modest overhead allows the secure NTT to be used in resource-constrained post-quantum devices.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The method could be adapted to protect other lattice-based primitives such as Dilithium or NTRU against similar control-flow Trojans.
  • Real silicon deployments would need additional validation against Trojans that adapt to the detection logic itself.
  • Layering this technique with existing data-path countermeasures would raise the bar for combined side-channel and fault attacks.

Load-bearing premise

The detection mechanisms can reliably identify Trojan-induced delays and control-flow changes without excessive false positives or missing adaptive attacks.

What would settle it

Insertion of a control-signal Trojan into the NTT on an Artix-7 FPGA followed by a run of Kyber that produces undetected or uncorrected faults in more than a small fraction of trials.

Figures

Figures reproduced from arXiv: 2601.22804 by Amlan Chakrabarti, Krishnendu Guha, Rourab Paul.

Figure 3
Figure 3. Figure 3: rd_en uBu_strt wr_en/uv_strt barrett_strt uv_rst barrett_rst polymem _ce rst CTRL_rst uBu_rst CSR[3] CSR[2] CSR[1] CSR[0] [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 1
Figure 1. Figure 1: Control and Status Signals of NTT RSR[3] RSR[2] RSR[1] RSR[0] 0 if rd_en==0 1 if rd_en==1 [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: Timing Diagram of Our Secure NTT memory read ω, U=α[j+k], α[j+k+i/2] V=ω Xα[j+k+i/2] % q using Barrett α[j+k]=U+V α[j+k+i/2]=U-V loop=0 loop=1 loop=log (n)Xn/2 -1 2 memory write α[j+k] & α[j+k+i/2] loop=2 memory read ω, U=α[j+k], α[j+k+i/2] V=ω Xα[j+k+i/2] % q using Barrett α[j+k]=U+V α[j+k+i/2]=U-V memory write α[j+k] & α[j+k+i/2] memory read ω, U=α[j+k], α[j+k+i/2] V=ω Xα[j+k+i/2] % q using Barrett α[j+k… view at source ↗
Figure 4
Figure 4. Figure 4: Pipeline Stages of proposed Secure NTT Polynomial Memory wr_en rd_en ce Bit reverser addr_rd_k0 addr_rd_k1 addr_wr_k0 addr_wr_k1 u=A[k0] A[k1] Barrett Reduction w memory UV Adder UV Sub CTRL uv_rst barrett_ctrl CTRL V U Buer u+v u-v Control Signals addr & data CFI CCC LM CSR signals c_fault ccc_fault LM NTT NTT_strt NTT_rst reversed-j j addr Gen k hl wj [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Architecture of Secure NTT with Fault Detection [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: Architecture of Secure NTT With Fault Correction [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 6
Figure 6. Figure 6: Bit Patcher Table importance of control-flow faults cf i_f aulti and unconven￾tional delays fault ccc_f aulti of i th NTT which is known as NT Ti . If control-flow faults cf i_f ault are more critical, set Wcf i > Wccc. If unconventional delays fault ccc_f ault are more critical, set Wccc > Wcf i. In our system, we use Wcf i = 0.5 and Wccc = 0.5. For the relocation of the NTT in measure III-A3, the bit pat… view at source ↗
Figure 8
Figure 8. Figure 8: Flow Diagram of Fault Correction Module for [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Connection of Fault Injector with Control Signals [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
read the original abstract

Number Theoretic Transform (NTT) is the most essential component for polynomial multiplications used in lattice-based Post-Quantum Cryptography (PQC) algorithms such as Kyber, Dilithium, NTRU etc. However, side-channel attacks (SCA) and hardware vulnerabilities in the form of hardware Trojans may alter control signals to disrupt the circuit's control flow and introduce unconventional delays in the critical hardware of PQC. Hardware Trojans, especially on control signals, are more low cost and impactful than data signals because a single corrupted control signal can disrupt or bypass entire computation sequences, whereas data faults usually cause only localized errors. On the other hand, adversaries can perform Soft Analytical Side Channel Attacks (SASCA) on the design using the inserted hardware Trojan. In this paper, we present a secure NTT architecture capable of detecting unconventional delays, control-flow disruptions, and SASCA, while providing an adaptive fault-correction methodology for their mitigation. Extensive simulations and implementations of our Secure NTT on Artix-7 FPGA with different Kyber variants show that our fault detection and correction modules can efficiently detect and correct faults whether caused unintentionally or intentionally by hardware Trojans with a high success rate, while introducing only modest area and time overheads.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 1 minor

Summary. The paper proposes a Trojan-resilient NTT architecture for lattice-based PQC (e.g., Kyber variants) that detects and corrects control-flow disruptions, unconventional timing delays, and SASCA induced by hardware Trojans on control signals. The design incorporates dedicated detection modules and an adaptive fault-correction methodology, evaluated via simulations and Artix-7 FPGA implementations that reportedly achieve high success rates with modest area and latency overheads.

Significance. If the detection and correction mechanisms prove reliable, the work would address a practical vulnerability in hardware PQC accelerators where low-cost control-signal Trojans can bypass entire computations or enable SASCA. The emphasis on reconfigurable platforms and combined protection against both unintentional faults and intentional Trojans is relevant to ongoing PQC standardization and deployment. However, the absence of quantitative metrics, baseline comparisons, and adversarial testing currently limits the assessed impact.

major comments (3)
  1. [Abstract] Abstract: the claim of 'high success rate' from 'extensive simulations and implementations on Artix-7 FPGA' is unsupported by any numerical detection rates, false-positive rates, error rates, or baseline comparisons against unprotected NTT designs, preventing assessment of the modules' actual effectiveness.
  2. [Evaluation] Evaluation section: no explicit fault model, Trojan placement strategy, or test coverage is described, and there is no evaluation against adaptive adversaries that deliberately tune delays or control signals to remain within the detection thresholds, leaving the central resilience claim untested.
  3. [Proposed architecture] Proposed architecture: the detection thresholds for 'unconventional delays' and control-signal anomalies are introduced as free parameters without a parameter-free derivation or sensitivity analysis, which directly affects the claimed ability to distinguish Trojan-induced faults from normal timing variation.
minor comments (1)
  1. [Abstract] The abstract and introduction could include a brief comparison table of area/latency overheads versus prior NTT hardening techniques.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the insightful comments. We address each major comment below and indicate the revisions we will make to strengthen the manuscript.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the claim of 'high success rate' from 'extensive simulations and implementations on Artix-7 FPGA' is unsupported by any numerical detection rates, false-positive rates, error rates, or baseline comparisons against unprotected NTT designs, preventing assessment of the modules' actual effectiveness.

    Authors: We agree with this observation. While the evaluation section provides detailed numerical results on detection rates, false-positive rates, and overhead comparisons from our Artix-7 FPGA implementations, the abstract does not summarize them. We will revise the abstract to include key quantitative metrics supporting the high success rate claim and baseline comparisons. revision: yes

  2. Referee: [Evaluation] Evaluation section: no explicit fault model, Trojan placement strategy, or test coverage is described, and there is no evaluation against adaptive adversaries that deliberately tune delays or control signals to remain within the detection thresholds, leaving the central resilience claim untested.

    Authors: We will revise the evaluation section to include an explicit description of the fault model, Trojan placement strategy on control signals, and test coverage details from our simulations. Regarding adaptive adversaries, while we evaluated a range of fault scenarios, we did not specifically test against adversaries that tune parameters to evade detection thresholds. We will add a discussion of this limitation and include sensitivity analysis to address the resilience claim more thoroughly. revision: partial

  3. Referee: [Proposed architecture] Proposed architecture: the detection thresholds for 'unconventional delays' and control-signal anomalies are introduced as free parameters without a parameter-free derivation or sensitivity analysis, which directly affects the claimed ability to distinguish Trojan-induced faults from normal timing variation.

    Authors: We will add a sensitivity analysis for the detection thresholds in the proposed architecture section. The thresholds are set based on timing analysis to distinguish normal variations from faults, and we will provide the derivation method and show how performance varies with different settings. This will strengthen the distinction between Trojan-induced faults and normal timing variation. revision: yes

Circularity Check

0 steps flagged

No circularity: design validated by direct FPGA experiments

full rationale

The paper proposes a hardware architecture for Trojan-resilient NTT with fault detection and correction modules. Its central claims rest on explicit FPGA implementations and simulations on Artix-7 with Kyber variants that report measured success rates and overheads. No equations, fitted parameters, self-citations, or uniqueness theorems are invoked; the derivation chain consists of standard hardware design steps followed by empirical measurement rather than any reduction of outputs to inputs by construction.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The design rests on domain assumptions about Trojan behavior and likely tuned detection thresholds; no new physical entities are postulated.

free parameters (1)
  • delay and control-signal detection thresholds
    Thresholds for identifying unconventional delays and disruptions are almost certainly tuned during simulation and FPGA testing to achieve the reported high success rate.
axioms (1)
  • domain assumption Hardware Trojans on control signals are low-cost and high-impact compared to data-path faults
    Explicitly stated in the abstract as the motivation for focusing on control-flow and timing protection.

pith-pipeline@v0.9.0 · 5527 in / 1215 out tokens · 31389 ms · 2026-05-16T09:31:53.675123+00:00 · methodology

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Reference graph

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