Behavioral-Level Simulation of Digital Readout for COFFEE at LHCb Upstream Pixel Tracker

Anqi Wang; Huimin Wu; Jianchun Wang; Lei Zhang; Leyi Li; Mingjie Feng; Xiaomin Wei; Xiaoxu Zhang; Yang Zhou; Yiming Li

arxiv: 2604.07318 · v1 · submitted 2026-04-08 · ⚛️ physics.ins-det

Behavioral-Level Simulation of Digital Readout for COFFEE at LHCb Upstream Pixel Tracker

Xiaoxu Zhang , Yang Zhou , Xiaomin Wei , Anqi Wang , Leyi Li , Yu Zhao , Zexuan Zhao , Huimin Wu

show 4 more authors

Mingjie Feng Lei Zhang Jianchun Wang Yiming Li

This is my paper

Pith reviewed 2026-05-10 17:19 UTC · model grok-4.3

classification ⚛️ physics.ins-det

keywords COFFEEHVCMOSpixel sensorcolumn-drain readoutbehavioral-level simulationLHCbdigital readoutBXID-sharing

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The pith

Behavioral simulation shows the column-drain readout for COFFEE pixel sensors achieves nearly 100% efficiency if each cycle is 100 ns or less.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper uses behavioral-level simulation to test the digital readout design for the COFFEE HVCMOS pixel sensor, which targets the high particle rates in the LHCb Upstream Pixel tracker. At rates up to 322.5 MHz per chip, the simulation evaluates how well the column-drain mechanism performs. It finds nearly complete efficiency when readout cycles stay within 100 nanoseconds. The study also determines the buffer and memory needs for a peripheral readout that uses BXID-sharing data format. These findings guide the actual chip implementation.

Core claim

The behavioral-level simulation results show that the column-drain readout mechanism achieves nearly 100% efficiency when the single readout cycle does not exceed 100 ns. The buffer depth and memory resources required for the peripheral readout adapted to the BXID-sharing data format are evaluated, providing guidance for the design of COFFEE. The column-drain readout mechanism was used in COFFEE3 fabricated in 2025, while the peripheral readout architecture adapted to the BXID-sharing data format is implemented in CHiR taped out in early 2026.

What carries the argument

Behavioral-level simulation of the column-drain readout mechanism combined with BXID-sharing peripheral architecture.

If this is right

The COFFEE sensor design can support the maximum hit rate of 322.5 MHz per chip with high efficiency.
Appropriate buffer depths can be chosen based on the simulation's memory resource evaluation.
The column-drain approach is suitable for incorporation into fabricated chips like COFFEE3.
The BXID-sharing format peripheral readout can be implemented in designs such as CHiR.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

If the model is accurate, behavioral simulations offer a fast way to iterate on readout designs before fabrication.
Setting a 100 ns upper limit on readout cycles implies a minimum clock frequency requirement for the digital logic.
Adoption in COFFEE3 and CHiR suggests this architecture could scale to other LHCb subdetectors facing similar rates.

Load-bearing premise

The behavioral-level model faithfully represents the actual digital circuitry behavior under the expected operating conditions and hit rates.

What would settle it

Fabricating the COFFEE3 chip and testing its readout efficiency directly with particle hits at rates up to 322.5 MHz per chip to verify if it stays near 100% for cycles under 100 ns.

Figures

Figures reproduced from arXiv: 2604.07318 by Anqi Wang, Huimin Wu, Jianchun Wang, Lei Zhang, Leyi Li, Mingjie Feng, Xiaomin Wei, Xiaoxu Zhang, Yang Zhou, Yiming Li, Yu Zhao, Zexuan Zhao.

**Figure 1.** Figure 1: (a) The row-column configuration of pixel array and the placement of peripheral readout. (b) The placement and orientation of the innermost chips adjacent to the beam. (a) (b) (c) [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 2.** Figure 2: The characteristics of MC hit events. (a) Hit rate distributions of two selected chips. (b) Distribution of hits/BXID for a single chip. (c) TOT distribution. The placement and orientation of the innermost chips adjacent to the beam are shown in [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Figure 3: The chip efficiency with different READ signal widths. (a) Chip 1. (b) Chip 2 [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 4.** Figure 4: Block diagram of the peripheral readout architecture adapted for the BXID-sharing data format. rate distribution shown in [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗

**Figure 5.** Figure 5: (a) The Normal Compact data format used by UP. (b) Schematic diagram illustrating the mechanism of the globally shared multi-bank circular buffer. (a) (b) (c) [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗

**Figure 6.** Figure 6: (a) Distribution of latency from hit to data packet arrival at the multi-bank circular buffer. (b) Efficiency loss when reducing memory resources by truncating the long tail. (c) Maximum occupancy of 16 FIFOs at the frontend of the multi-bank circular buffer. save 39.3% and 40.8% of the bits, respectively, when using the Normal Compact format. The key to realizing the BXID sharing is the globally shared mu… view at source ↗

read the original abstract

COFFEE series is a HVCMOS pixel sensor using the advanced 55 nm process, currently being developed for the Upstream Pixel (UP) tracker of the LHCb Upgrade II. To ensure that COFFEE will be able to handle the particle hit rates at UP tracker, which reach a maximum of 322.5 MHz/chip, detailed simulation of the digital readout circuitry was performed. Simulation results show that the column-drain readout mechanism achieves nearly 100\% efficiency when the single readout cycle does not exceed 100 ns. Meanwhile, the buffer depth and memory resources required for the peripheral readout adapted to the BXID-sharing data format are also evaluated. These provide guidance for the design of COFFEE. The column-drain readout mechanism was used in COFFEE3 (fabricated in 2025), while the peripheral readout architecture adapted to the BXID-sharing data format is implemented in CHiR (taped out in early 2026).

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

Behavioral sims claim near-100% efficiency for COFFEE column-drain readout under 100 ns cycles, but the model has no visible validation against 55 nm hardware effects.

read the letter

The main thing here is that the paper runs behavioral simulations of the digital readout for the COFFEE HVCMOS sensor and reports nearly 100% efficiency with column-drain readout as long as the cycle time stays at or below 100 ns at the 322.5 MHz per chip hit rate expected for the LHCb Upstream Pixel tracker. They also size the buffers and memory for the peripheral readout that uses the BXID-sharing format. The work notes that the column-drain part is already in the fabricated COFFEE3 chip and the peripheral architecture is in CHiR, which taped out recently. That connection to actual silicon steps is useful. The paper does a straightforward job of turning the hit-rate requirement into concrete numbers on cycle time and buffer depth that can steer the final design. It is the kind of targeted engineering check that detector groups need before tape-out. The clear limitation is the behavioral model. Nothing in the text shows how the model was checked against post-layout extraction, gate-level timing, or measurements from prior COFFEE prototypes. At 55 nm, unmodeled effects such as process variation, IR drop, and analog-digital coupling could shift the real timing, yet the simulation treats the abstraction as sufficient without error bounds. The efficiency number therefore rests on untested assumptions rather than demonstrated behavior. This paper is for the LHCb pixel upgrade team and a handful of other groups doing high-rate pixel readouts. A reader outside that circle will not find broad new methods or physics results. It is worth sending for peer review because the topic directly affects an active experiment upgrade and the numbers could influence real design decisions; referees can ask for the missing validation steps.

Referee Report

2 major / 1 minor

Summary. The manuscript describes behavioral-level simulations of the digital readout circuitry for the COFFEE HVCMOS pixel sensor (55 nm process) intended for the LHCb Upstream Pixel tracker. It reports that the column-drain readout achieves nearly 100% efficiency when the single readout cycle time is at most 100 ns at the maximum hit rate of 322.5 MHz per chip. The work also evaluates the required buffer depth and memory resources for a peripheral readout architecture adapted to the BXID-sharing data format. The column-drain mechanism is noted as implemented in the COFFEE3 prototype (fabricated 2025) and the peripheral architecture in CHiR (taped out 2026).

Significance. If the behavioral model is shown to be faithful to the actual 55 nm HVCMOS timing and hit-rate response, the results would provide concrete pre-silicon guidance for high-rate pixel readout design in HEP experiments. The efficiency threshold and resource estimates could directly inform architecture choices for LHCb Upgrade II and similar trackers. The work's value is currently limited by the absence of any anchoring of the model to hardware, post-layout extraction, or prior prototypes.

major comments (2)

The central efficiency claim (nearly 100% for cycle time ≤100 ns) rests entirely on an unvalidated behavioral model. The manuscript provides no details on how gate delays, analog front-end coupling, power-grid IR drop, or 55 nm process variation were bounded or cross-checked against post-layout netlists or measurements from earlier COFFEE prototypes. This directly undermines in the reported efficiency number as a property of the eventual silicon rather than an artifact of the chosen abstraction level.
No information is given on the hit-rate model, hit clustering assumptions, or exact timing parameters used to generate the simulation results. Without these, it is impossible to assess whether the ~100% efficiency holds under realistic LHCb UP tracker conditions or is sensitive to small changes in the input distribution.

minor comments (1)

The abstract and text would benefit from explicit statements of the simulation tool, clock frequency (322.5 MHz is mentioned but not tied to a specific clock domain), and any simplifications made in the behavioral description.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the thorough review and valuable comments, which highlight important aspects of model validation and simulation transparency. We address each major comment below and will make targeted revisions to strengthen the manuscript.

read point-by-point responses

Referee: The central efficiency claim (nearly 100% for cycle time ≤100 ns) rests entirely on an unvalidated behavioral model. The manuscript provides no details on how gate delays, analog front-end coupling, power-grid IR drop, or 55 nm process variation were bounded or cross-checked against post-layout netlists or measurements from earlier COFFEE prototypes. This directly undermines in the reported efficiency number as a property of the eventual silicon rather than an artifact of the chosen abstraction level.

Authors: We agree that the behavioral model is an abstraction and does not incorporate low-level effects such as detailed gate delays, analog coupling, IR drop, or process variation, which would require post-layout extraction or silicon measurements. The model employs conservative timing estimates derived from the 55 nm process design kit specifications to evaluate architectural feasibility at the behavioral level. The column-drain readout has been implemented in the COFFEE3 prototype (fabricated 2025), providing a path for future hardware validation, while the peripheral architecture is in CHiR (taped out 2026). We will add a new subsection explicitly discussing the model's scope, limitations, and conservative assumptions to clarify that the efficiency results represent an upper-bound architectural assessment rather than a precise silicon prediction. revision: partial
Referee: No information is given on the hit-rate model, hit clustering assumptions, or exact timing parameters used to generate the simulation results. Without these, it is impossible to assess whether the ~100% efficiency holds under realistic LHCb UP tracker conditions or is sensitive to small changes in the input distribution.

Authors: We will revise the manuscript to include a dedicated section on the simulation methodology. This will detail the hit-rate model (Poisson arrivals at up to 322.5 MHz per chip, matching the maximum expected rate for the LHCb Upstream Pixel tracker), the assumption of independent random hits without clustering (chosen as a conservative worst-case for readout contention), and the exact timing parameters (readout cycle times swept from 50 ns to 200 ns, with buffer depths and memory sizing evaluated for the BXID-sharing format). These parameters are derived from LHCb Upgrade II specifications and standard behavioral modeling practices in SystemVerilog. revision: yes

Circularity Check

0 steps flagged

No significant circularity in simulation-based claims

full rationale

This is a forward simulation study of digital readout circuitry using a behavioral-level model. The reported efficiency results (nearly 100% for readout cycles ≤100 ns) are computed outputs from the simulation under given hit rates and conditions, not predictions derived by fitting to the same data or by self-definition. The model assumptions are stated as inputs, and the results follow from executing the model. No self-citation chains or uniqueness theorems are invoked to force the architecture. The work is self-contained against external benchmarks as a design guidance tool, with the actual silicon validation noted as future (COFFEE3 fabricated in 2025).

Axiom & Free-Parameter Ledger

2 free parameters · 1 axioms · 0 invented entities

The simulation depends on unstated details of the behavioral model and assumptions about particle hit distributions and timing.

free parameters (2)

maximum hit rate = 322.5 MHz/chip
Stated as the target rate the sensor must handle.
readout cycle time threshold = 100 ns
Condition for achieving nearly 100% efficiency.

axioms (1)

domain assumption The behavioral model of the digital readout circuitry is sufficiently accurate to predict real hardware performance.
Central to trusting the simulation results for design guidance.

pith-pipeline@v0.9.0 · 5504 in / 1234 out tokens · 66370 ms · 2026-05-10T17:19:26.629131+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

Simulation results show that the column-drain readout mechanism achieves nearly 100% efficiency when the single readout cycle does not exceed 100 ns.
IndisputableMonolith/Foundation/AlexanderDuality.lean alexander_duality_circle_linking unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

The row-column configuration of the pixel array... 128×360 pixels

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

6 extracted references · 6 canonical work pages

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