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arxiv: 2604.16699 · v1 · submitted 2026-04-17 · 💻 cs.CR

Glitch in the Sky: Exploiting Voltage Fault Injection in UAV Flight Controllers

Yun-Ping Hsiao , Yanda Li , Youssef Gamal , Halima Bouzidi , Mohammad Abudllah Al Faruque This is my paper

Pith reviewed 2026-05-10 07:40 UTC · model grok-4.3

classification 💻 cs.CR
keywords voltage fault injectionUAV securityfail-safe mechanismshardware attackscyber-physical systemsautopilot vulnerabilitiestiming attackssafety response suppression
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The pith

Voltage glitching suppresses fail-safe activation in UAV flight controllers at critical moments.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper investigates whether voltage fault injection can disrupt the fail-safe logic inside UAV autopilots. It combines software simulation of faults with hardware experiments that deliver controlled voltage glitches to the processor executing that logic. The work identifies narrow timing windows where the glitches prevent or change safety responses, including blocking emergency failsafe engagement. A sympathetic reader would care because successful attacks of this kind would let an adversary interfere with an autonomous vehicle's safety systems using only external hardware disturbances.

Core claim

The paper claims that voltage glitches applied at specific timings to the microcontroller running UAV autopilot fail-safe logic can suppress or alter safety responses, such as disabling emergency failsafe activation during critical periods, which may enable hijacking.

What carries the argument

Voltage glitch fault injection applied at precise execution timings to disrupt fail-safe mode routines in the flight controller.

Load-bearing premise

The chosen fail-safe modes and timing windows are representative of real-world UAV deployments and the laboratory glitching method accurately reproduces faults an attacker could deliver in the field.

What would settle it

A production UAV test in which voltage glitches are applied at the identified critical timings yet the emergency failsafe activates and functions normally.

Figures

Figures reproduced from arXiv: 2604.16699 by Halima Bouzidi, Mohammad Abudllah Al Faruque, Yanda Li, Youssef Gamal, Yun-Ping Hsiao.

Figure 1
Figure 1. Figure 1: A voltage fault injection attack and its potential impacts [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Architecture of a PX4-based UAV system showing the [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Integrated simulation workflow. A. Software Simulation ARMORY is an open-source, automated framework de￾signed to perform fault simulation on ARM-M binaries. It emulates the behavior of ARM processors, allowing for the injection of various fault models at the machine-code level to analyze their impact on program execution. Because the STM32 microcontroller, commonly used in PX4 flight controllers, is based… view at source ↗
Figure 6
Figure 6. Figure 6: Workflow illustrating the coordinated fault injection [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: Fault injection outcomesin RC Signal Loss scenario [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 7
Figure 7. Figure 7: Temporal distribution of successful faults in RC Signal [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 10
Figure 10. Figure 10: Distribution of fault-induced actions in RC Signal [PITH_FULL_IMAGE:figures/full_fig_p007_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Temporal distribution of successful faults in Battery [PITH_FULL_IMAGE:figures/full_fig_p007_11.png] view at source ↗
Figure 13
Figure 13. Figure 13: Temporal distribution of fault effects categorized by [PITH_FULL_IMAGE:figures/full_fig_p008_13.png] view at source ↗
Figure 16
Figure 16. Figure 16: Temporal distribution of successful faults within [PITH_FULL_IMAGE:figures/full_fig_p008_16.png] view at source ↗
Figure 14
Figure 14. Figure 14: Distribution of specific observed Failsafe Action [PITH_FULL_IMAGE:figures/full_fig_p008_14.png] view at source ↗
Figure 17
Figure 17. Figure 17: Distribution of aggregate fault outcomes (Success, [PITH_FULL_IMAGE:figures/full_fig_p008_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: Temporal distribution of fault effects categorized by [PITH_FULL_IMAGE:figures/full_fig_p009_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Distribution of specific observed outcomes versus [PITH_FULL_IMAGE:figures/full_fig_p009_19.png] view at source ↗
read the original abstract

As Cyber-Physical Systems (CPS) become increasingly pervasive and autonomous, ensuring the resilience of their embedded logic is critical to maintaining safety and integrity. Among the most stealthy and damaging threats are non-invasive fault injection attacks, where hardware-level disturbances propagate into software execution and compromise control logic. In this paper, we investigate the susceptibility of Unmanned Aerial Vehicle (UAV) autopilot fail-safe mechanisms to voltage glitch fault injection. We introduce a dual evaluation approach: software-based fault simulation using ARMORY and hardware-based experiments with a voltage glitching platform (Chip-Whisperer), applying controlled and timely faults to an STM32 microcontroller running UAV-Autopilot fail-safe logic. Our targeted analysis of specific fail-safe modes uncovers timing-sensitive vulnerabilities that can suppress or alter safety responses, such as disabling emergency failsafe activation at critical moments, potentially enabling UAV hijacking. Furthermore, we validate software-based fault injection results against real hardware behavior, demonstrating how simulated attacks translate into tangible risks for CPS security and reliability.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The paper claims that voltage glitch fault injection attacks can suppress or alter specific fail-safe modes in UAV autopilot software (UAV-Autopilot on STM32), demonstrated via a dual approach of software simulation with ARMORY and hardware experiments using the Chip-Whisperer platform. Targeted timing-sensitive glitches are shown to disable emergency failsafe activation, with simulation results validated against isolated hardware behavior, raising the possibility of enabling UAV hijacking.

Significance. If the central empirical findings hold under realistic conditions, the work would usefully extend fault-injection research to safety-critical CPS, particularly by showing how hardware glitches can interfere with fail-safe logic rather than just crashing execution. The dual simulation-plus-hardware validation is a methodological strength that helps bridge abstract models and concrete microcontroller behavior.

major comments (3)
  1. [Hardware Experiments] Hardware Experiments section: all voltage-glitch results are obtained on an isolated STM32 development board under controlled lab conditions; no data or setup is presented showing that comparable faults can be induced on a battery-powered, flying UAV while respecting physical access limits, power-rail noise, and stealth constraints. This directly affects the claim that the demonstrated glitches translate to hijacking risk in operational deployments.
  2. [Fail-safe Mode Analysis and Results] Fail-safe Mode Analysis and Results sections: timing windows for successful glitches appear to be identified post-hoc from simulation traces; the manuscript provides no evidence that an attacker could locate these windows in a black-box setting or that the windows remain effective across different UAV-Autopilot configurations, firmware versions, or environmental conditions.
  3. [Validation] Validation subsection: while the paper states that ARMORY simulation results are validated against hardware, no quantitative agreement metrics (success-rate tables, error bars, statistical tests, or full raw data) are supplied, leaving the reliability of the simulation-to-hardware mapping unclear and weakening the dual-evaluation claim.
minor comments (2)
  1. [Abstract and Introduction] The abstract and introduction would benefit from explicitly naming the specific UAV-Autopilot version, STM32 model, and fail-safe modes examined so readers can assess representativeness.
  2. [Figures and Experiments] Figure captions and experimental descriptions should include the exact glitch parameters (voltage offset, duration, trigger offset) used in each successful trial rather than qualitative descriptions.

Simulated Author's Rebuttal

3 responses · 1 unresolved

We thank the referee for the constructive comments on our manuscript. We address each of the major comments below, indicating where revisions will be made to strengthen the paper.

read point-by-point responses

  1. Referee: [Hardware Experiments] Hardware Experiments section: all voltage-glitch results are obtained on an isolated STM32 development board under controlled lab conditions; no data or setup is presented showing that comparable faults can be induced on a battery-powered, flying UAV while respecting physical access limits, power-rail noise, and stealth constraints. This directly affects the claim that the demonstrated glitches translate to hijacking risk in operational deployments.

    Authors: We agree that our hardware experiments were performed on an isolated STM32 board in a controlled laboratory environment. This setup was chosen to allow precise control over the fault injection parameters and to ensure safety. We did not conduct experiments on a flying UAV due to the practical difficulties and safety concerns associated with inducing faults during flight. In the revised manuscript, we will add a discussion of these limitations in the Hardware Experiments section, including considerations for power-rail noise, physical access, and stealth in operational settings. We will also emphasize that our results highlight a potential vulnerability that warrants further investigation in realistic deployments. revision: partial

  2. Referee: [Fail-safe Mode Analysis and Results] Fail-safe Mode Analysis and Results sections: timing windows for successful glitches appear to be identified post-hoc from simulation traces; the manuscript provides no evidence that an attacker could locate these windows in a black-box setting or that the windows remain effective across different UAV-Autopilot configurations, firmware versions, or environmental conditions.

    Authors: The timing windows were identified through systematic simulation using ARMORY by analyzing the execution traces of the fail-safe logic. Regarding black-box settings, since UAV-Autopilot is open-source, an attacker could potentially replicate the simulation approach or use similar profiling techniques. However, we recognize the need for more explicit discussion on this. In the revision, we will clarify the methodology for identifying the windows and add a note on the attacker assumptions, including potential variations across firmware versions and conditions. We will also discuss how environmental factors might affect the windows. revision: partial

  3. Referee: [Validation] Validation subsection: while the paper states that ARMORY simulation results are validated against hardware, no quantitative agreement metrics (success-rate tables, error bars, statistical tests, or full raw data) are supplied, leaving the reliability of the simulation-to-hardware mapping unclear and weakening the dual-evaluation claim.

    Authors: We acknowledge that the validation section lacks quantitative metrics. To address this, we will include in the revised manuscript success rate tables comparing simulation and hardware results, along with any available error analysis or statistical comparisons. This will provide a clearer picture of the agreement between the two evaluation methods and strengthen the dual-evaluation approach. revision: yes

standing simulated objections not resolved
  • No experimental data is available demonstrating voltage glitches on a battery-powered, flying UAV.

Circularity Check

0 steps flagged

Empirical hardware/software attack demo contains no derivation chain

full rationale

The manuscript presents only experimental results: ARMORY simulation of faults on UAV-Autopilot fail-safe logic plus Chip-Whisperer voltage glitching on an STM32 board. No equations, fitted parameters, predictions derived from inputs, or self-citation chains appear in the abstract or described methodology. All claims rest on direct observation of hardware behavior under controlled conditions rather than any reduction to prior self-referential results.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No free parameters, axioms, or invented entities are introduced; the paper rests on standard fault-injection assumptions and existing hardware platforms.

pith-pipeline@v0.9.0 · 5493 in / 1034 out tokens · 27743 ms · 2026-05-10T07:40:12.836294+00:00 · methodology

discussion (0)

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Reference graph

Works this paper leans on

42 extracted references · 42 canonical work pages

  1. [1]

    Fault injection techniques and tools,

    M.-C. Hsueh, T. K. Tsai, and R. K. Iyer, “Fault injection techniques and tools,”Computer, vol. 30, no. 4, pp. 75–82, 1997

    work page 1997

  2. [2]

    Adaptive data fusion for state estimation and control of power grids under attack,

    T. Mortlock and M. A. Al Faruque, “Adaptive data fusion for state estimation and control of power grids under attack,”IEEE Transactions on Industrial Informatics, vol. 20, no. 9, pp. 11 115–11 126, 2024

    work page 2024

  3. [3]

    Sargolzaei, A

    A. Sargolzaei, A. Abbaspour, M. A. Al Faruque, A. Salah Eddin, and K. Yen,Security Challenges of Networked Control Systems. Cham: Springer International Publishing, 2018, pp. 77–95. [Online]. Available: https://doi.org/10.1007/978-3-319-74412-4 6

    work page doi:10.1007/978-3-319-74412-4 2018

  4. [4]

    T- bfa: Targeted bit-flip adversarial weight attack,

    A. S. Rakin, Z. He, J. Li, F. Yao, C. Chakrabarti, and D. Fan, “T- bfa: Targeted bit-flip adversarial weight attack,”IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 44, no. 11, pp. 7928– 7939, 2021

    work page 2021

  5. [5]

    Escalating privileges in linux using voltage fault injection,

    N. Timmers and C. Mune, “Escalating privileges in linux using voltage fault injection,” in2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC). IEEE, 2017, pp. 1–8

    work page 2017

  6. [6]

    Flipping bits in memory without accessing them: an experimental study of dram disturbance errors,

    Y . Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu, “Flipping bits in memory without accessing them: an experimental study of dram disturbance errors,”SIGARCH Comput. Archit. News, vol. 42, no. 3, p. 361–372, Jun. 2014. [Online]. Available: https://doi.org/10.1145/2678373.2665726

    work page doi:10.1145/2678373.2665726 2014

  7. [7]

    Low voltage fault attacks on the rsa cryptosystem,

    A. Barenghi, G. Bertoni, E. Parrinello, and G. Pelosi, “Low voltage fault attacks on the rsa cryptosystem,” in2009 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC). IEEE, 2009, pp. 23–31

    work page 2009

  8. [8]

    Modern hardware security: A review of attacks and countermeasures,

    J. Mishra and S. K. Sahay, “Modern hardware security: A review of attacks and countermeasures,”arXiv preprint arXiv:2501.04394, 2025

    work page arXiv 2025

  9. [9]

    Design and analysis of clock fault injection for aes,

    P. Yang, F. Luo, Q. Ou, and D. Zhou, “Design and analysis of clock fault injection for aes,” in2020 International Conference on Computer Communication and Network Security (CCNS). IEEE, 2020, pp. 87–91

    work page 2020

  10. [10]

    Electromagnetic fault injection: towards a fault model on a 32-bit microcontroller,

    N. Moro, A. Dehbaoui, K. Heydemann, B. Robisson, and E. Encrenaz, “Electromagnetic fault injection: towards a fault model on a 32-bit microcontroller,” in2013 Workshop on Fault Diagnosis and Tolerance in Cryptography. Ieee, 2013, pp. 77–88

    work page 2013

  11. [11]

    Com- bined fault injection and real-time side-channel analysis for android secure-boot bypassing,

    C. Fanjas, C. Gaine, D. Aboulkassimi, S. Ponti ´e, and O. Potin, “Com- bined fault injection and real-time side-channel analysis for android secure-boot bypassing,” inSmart Card Research and Advanced Appli- cations, I. Buhan and T. Schneider, Eds. Cham: Springer International Publishing, 2023, pp. 25–44

    work page 2023

  12. [12]

    Security-aware functional modeling of cyber-physical systems,

    J. Wan, A. Canedo, and M. A. Al Faruque, “Security-aware functional modeling of cyber-physical systems,” in2015 IEEE 20th Conference on Emerging Technologies & Factory Automation (ETFA), 2015, pp. 1–4

    work page 2015

  13. [13]

    Oligo-snoop: a non-invasive side chan- nel attack against dna synthesis machines,

    S. Faezi, S. R. Chhetri, A. V . Malawade, J. C. Chaput, W. Grover, P. Brisk, and M. A. Al Faruque, “Oligo-snoop: a non-invasive side chan- nel attack against dna synthesis machines,” inNetwork and Distributed Systems Security (NDSS) Symposium 2019, 2019

    work page 2019

  14. [14]

    Physical layer key generation: Securing wireless communication in automotive cyber- physical systems,

    J. Wan, A. Lopez, and M. A. A. Faruque, “Physical layer key generation: Securing wireless communication in automotive cyber- physical systems,”ACM Trans. Cyber-Phys. Syst., vol. 3, no. 2, Oct

    work page

  15. [15]

    Available: https://doi.org/10.1145/3140257

    [Online]. Available: https://doi.org/10.1145/3140257

    work page doi:10.1145/3140257

  16. [16]

    Information leakage- aware computer-aided cyber-physical manufacturing,

    S. R. Chhetri, S. Faezi, and M. A. Al Faruque, “Information leakage- aware computer-aided cyber-physical manufacturing,”IEEE Transac- tions on Information Forensics and Security, vol. 13, no. 9, pp. 2333– 2344, 2018

    work page 2018

  17. [17]

    Fix the leak! an information leakage aware secured cyber- physical manufacturing system,

    ——, “Fix the leak! an information leakage aware secured cyber- physical manufacturing system,” inDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, pp. 1408–1413

    work page 2017

  18. [18]

    Security trends and advances in manufacturing systems in the era of industry 4.0,

    S. R. Chhetri, N. Rashid, S. Faezi, and M. A. Al Faruque, “Security trends and advances in manufacturing systems in the era of industry 4.0,” in2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2017, pp. 1039–1046

    work page 2017

  19. [19]

    A security perspective on battery systems of the internet of things,

    A. B. Lopez, K. Vatanparvar, A. P. Deb Nath, S. Yang, S. Bhunia, and M. A. Al Faruque, “A security perspective on battery systems of the internet of things,”Journal of Hardware and Systems Security, vol. 1, pp. 188–199, 2017

    work page 2017

  20. [20]

    Cross-domain security of cyber-physical systems,

    S. R. Chhetri, J. Wan, and M. A. Al Faruque, “Cross-domain security of cyber-physical systems,” in2017 22nd Asia and South Pacific design automation conference (ASP-DAC). IEEE, 2017, pp. 200–205

    work page 2017

  21. [21]

    Thermal side-channel forensics in additive manufacturing systems,

    S. R. Chhetri, S. Faezi, A. Canedo, and M. A. Al Faruque, “Thermal side-channel forensics in additive manufacturing systems,” in2016 ACM/IEEE 7th International Conference on Cyber-Physical Systems (ICCPS). IEEE, 2016, pp. 1–1

    work page 2016

  22. [22]

    Modeling and simulation of cyberattacks for resilient cyber-physical systems,

    N. Rashid, J. Wan, G. Quiros, A. Canedo, and M. A. Al Faruque, “Modeling and simulation of cyberattacks for resilient cyber-physical systems,” in2017 13th IEEE Conference on Automation Science and Engineering (CASE). IEEE, 2017, pp. 988–993

    work page 2017

  23. [23]

    Models, abstractions, and architectures: The missing links in cyber- physical systems,

    B. Balaji, M. A. Al Faruque, N. Dutt, R. Gupta, and Y . Agarwal, “Models, abstractions, and architectures: The missing links in cyber- physical systems,” inProceedings of the 52nd Annual Design Automa- tion Conference, 2015, pp. 1–6

    work page 2015

  24. [24]

    Cross-layer security of embedded and cyber-physical systems,

    M. A. Al Faruque, “Cross-layer security of embedded and cyber-physical systems,” inProceedings of the 2022 ACM CCS Workshop on Additive Manufacturing (3D Printing) Security, 2022, pp. 39–40

    work page 2022

  25. [25]

    Flytrap: Physical distance-pulling attack towards camera-based autonomous target tracking systems,

    S. Xie, M. H. Fakih, J. Lu, F. Alshammari, N. Wang, T. Sato, H. Bouzidi, M. A. A. Faruque, and Q. A. Chen, “Flytrap: Physical distance-pulling attack towards camera-based autonomous target tracking systems,”arXiv preprint arXiv:2509.20362, 2025

    work page arXiv 2025

  26. [26]

    Survey of low-power electric vehicles: A design automation perspec- tive,

    N. Chang, M. Al Faruque, Z. Shao, C. J. Xue, Y . Chen, and D. Baek, “Survey of low-power electric vehicles: A design automation perspec- tive,”IEEE Design & Test, vol. 35, no. 6, pp. 44–70, 2018

    work page 2018

  27. [27]

    Rampo: A cegar-based integration of binary code anal- ysis and system falsification for cyber-kinetic vulnerability detection,

    K. Tsujioet al., “Rampo: A cegar-based integration of binary code anal- ysis and system falsification for cyber-kinetic vulnerability detection,” in2024 ACM/IEEE 15th International Conference on Cyber-Physical Systems (ICCPS), 2024, pp. 45–54

    work page 2024

  28. [28]

    Lightweight cyberattack intrusion detection system for unmanned aerial vehicles using recurrent neural net- works,

    W.-C. Hsu, “Lightweight cyberattack intrusion detection system for unmanned aerial vehicles using recurrent neural net- works,” Ph.D. dissertation, Purdue University, 2021. [Online]. Available: https://www.proquest.com/dissertations-theses/lightweight- cyberattack-intrusion-detection/docview/2838331386/se-2

    work page arXiv 2021

  29. [29]

    Cybersecurity of unmanned aerial vehicles: A survey,

    Z. Yu, Z. Wang, J. Yu, D. Liu, H. H. Song, and Z. Li, “Cybersecurity of unmanned aerial vehicles: A survey,”IEEE Aerospace and Electronic Systems Magazine, vol. 39, no. 9, pp. 182–215, 2023

    work page 2023

  30. [30]

    Pgfuzz: Policy-guided fuzzing for robotic vehicles

    H. Kim, M. O. Ozmen, A. Bianchi, Z. B. Celik, and D. Xu, “Pgfuzz: Policy-guided fuzzing for robotic vehicles.” inNDSS, 2021

    work page 2021

  31. [31]

    Enforcing mavlink safety & security properties via refined multiparty session types,

    A. Amorim, M. Taylor, T. Kann, W. L. Harrison, G. T. Leavens, and L. Joneckis, “Enforcing mavlink safety & security properties via refined multiparty session types,” 2025. [Online]. Available: https://arxiv.org/abs/2501.18874

    work page arXiv 2025

  32. [32]

    Fuzzing drones for anomaly detection: A systematic literature review,

    V . K. Malviya, W. Minn, L. K. Shar, and L. Jiang, “Fuzzing drones for anomaly detection: A systematic literature review,”Computers & Security, p. 104157, 2024

    work page 2024

  33. [33]

    An analysis of gps spoofing attack and efficient approach to spoofing detection in px4,

    J. H. Jung, M. Y . Hong, H. Choi, and J. W. Yoon, “An analysis of gps spoofing attack and efficient approach to spoofing detection in px4,” IEEE Access, 2024

    work page 2024

  34. [34]

    Oops..! i glitched it again! how to Multi-Glitch the Glitching- Protections on ARM TrustZone-M,

    X. M. Saß, R. Mitev, and A.-R. Sadeghi, “Oops..! i glitched it again! how to Multi-Glitch the Glitching- Protections on ARM TrustZone-M,” in32nd USENIX Security Symposium (USENIX Security 23). Anaheim, CA: USENIX Association, Aug. 2023, pp. 6239–6256. [Online]. Available: https://www.usenix.org/conference/usenixsecurity23/presentation/sass

    work page 2023

  35. [35]

    On the effects of clock and power supply tampering on two microcontroller platforms,

    T. Korak and M. Hoefler, “On the effects of clock and power supply tampering on two microcontroller platforms,” in2014 Workshop on Fault Diagnosis and Tolerance in Cryptography. IEEE, 2014, pp. 8–17

    work page 2014

  36. [36]

    Fault injection using crowbars on embedded systems,

    C. O’Flynn, “Fault injection using crowbars on embedded systems,” IACR Cryptol. ePrint Arch., vol. 2016, p. 810, 2016. [Online]. Available: https://api.semanticscholar.org/CorpusID:8502986

    work page 2016

  37. [37]

    How practical are fault injection attacks, really?

    J. Breier and X. Hou, “How practical are fault injection attacks, really?” IEEE Access, vol. 10, pp. 113 122–113 130, 2022

    work page 2022

  38. [38]

    Px4: A node-based mul- tithreaded open source robotics framework for deeply embedded plat- forms,

    L. Meier, D. Honegger, and M. Pollefeys, “Px4: A node-based mul- tithreaded open source robotics framework for deeply embedded plat- forms,” in2015 IEEE International Conference on Robotics and Au- tomation (ICRA), 2015, pp. 6235–6240

    work page 2015

  39. [39]

    (2025) Safety (failsafe) configuration

    PX4 Autopilot Developers. (2025) Safety (failsafe) configuration. [Online]. Available: https://docs.px4.io/main/en/config/safety.html

    work page 2025

  40. [40]

    Armory: Fully automated and exhaustive fault simulation on arm-m binaries,

    M. Hoffmann, F. Schellenberg, and C. Paar, “Armory: Fully automated and exhaustive fault simulation on arm-m binaries,”IEEE Transactions on Information Forensics and Security, vol. 16, pp. 1058–1073, 2021

    work page 2021

  41. [41]

    V oltage fault injection on a modern rpi sbc,

    C. O’Flynn, “V oltage fault injection on a modern rpi sbc,” https://circuitcellar.com/research-design-hub/design-solutions/voltage- fault-injection-on-a-modern-rpi-sbc/, 2021

    work page 2021

  42. [42]

    V oltage glitching a raspberry pi with the chipwhisperer,

    ——, “V oltage glitching a raspberry pi with the chipwhisperer,” https://www.youtube.com/watch?v=dVkCNiM0PL8, 2020

    work page 2020