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arxiv: 2604.20916 · v1 · submitted 2026-04-22 · 💻 cs.AR

AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout

Xian Rong Qin , Yong Zhang , Ying Hu , Tao Su , Bo-Wen Jia , Ning Xu This is my paper

Pith reviewed 2026-05-09 23:52 UTC · model grok-4.3

classification 💻 cs.AR
keywords analog IC designlarge language modelsdesign automationschematic image processingnetlist generationparameter optimizationphysical design automation
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The pith

Large language models automate analog IC design end-to-end from schematic image to physical layout.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents AnalogMaster as a unified LLM-based framework that converts unstructured circuit schematic images into netlists, optimizes device parameters, and completes placement and routing. This pipeline tackles the coupled performance metrics and image-based inputs that have kept prior tools limited to single stages of analog design. If the approach holds, it would allow the full analog design flow to proceed with far less manual correction than current methods require. Experiments on 15 circuits of different complexities show the framework delivering high completion rates across several large language models.

Core claim

AnalogMaster is an extensible LLM-based framework that enables end-to-end automation of analog IC design through a unified pipeline spanning circuit image-to-netlist generation, parameter optimization, placement, and routing. It integrates a joint reasoning mechanism that leverages in-context learning and intent reasoning to achieve accurate image-to-netlist conversion, along with a parameter search agent that uses self-enhanced prompt engineering and context truncation for device sizing and downstream physical design. On 15 representative circuits, GPT-5 reaches 92.9 percent success on Pass@1 and 99.9 percent on Pass@5.

What carries the argument

The unified LLM pipeline that combines joint reasoning for image-to-netlist conversion with a self-enhanced prompt engineering agent for parameter search and physical design steps.

If this is right

  • The full design flow can be completed with minimal manual intervention for circuits of varying complexity.
  • A single framework captures end-to-end performance effects rather than optimizing isolated stages.
  • Multiple large language models can be plugged into the same extensible pipeline.
  • High Pass@1 and Pass@5 success rates demonstrate practical robustness on representative test cases.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same image-to-layout pipeline could be tested on mixed-signal or RF circuits where schematic images are equally unstructured.
  • Adding direct links to circuit simulators inside the parameter agent might further reduce the need for external verification steps.
  • Success on 15 circuits suggests the method may scale to libraries of standard analog blocks used in consumer electronics.

Load-bearing premise

Large language models can reliably interpret unstructured schematic images and jointly manage strongly coupled analog performance metrics across the entire flow without needing substantial manual fixes.

What would settle it

Running the framework on a new set of complex analog circuits where image-to-netlist conversion produces invalid netlists or optimized layouts fail to meet performance specifications without human edits.

Figures

Figures reproduced from arXiv: 2604.20916 by Bo-Wen Jia, Ning Xu, Tao Su, Xian Rong Qin, Ying Hu, Yong Zhang.

Figure 1
Figure 1. Figure 1: Workflows of AnalogMaster: The circuit image, preprocessed via YOLO-based detection and connectivity analysis, is converted into a netlist using the proposed joint reasoning mechanism. A parameter search agent compresses the device parameter space, followed by BO for sizing, SA for placement, and A* for routing—enabling a fully automated design flow. to non-functional ones, are discarded. Each valid connec… view at source ↗
Figure 2
Figure 2. Figure 2: The process flow for circuit image analysis. (a) Original circuit image. (b) YOLO-based detection of components in the circuit. (c) Text [PITH_FULL_IMAGE:figures/full_fig_p008_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Overview of the Joint Reasoning workflow. Three heterogeneous inputs are processed via parallel MLLM reasoning branches, followed [PITH_FULL_IMAGE:figures/full_fig_p009_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: A prompt guiding the MLLM to follow the CoT approach for sequentially analyzing a circuit image and extracting a netlist. The diagram Prompti Completely Wrong Donepezil [PITH_FULL_IMAGE:figures/full_fig_p010_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Illustration of the multimodal context learning process. First, reference images and CoT prompts are input into the MLLM to establish a [PITH_FULL_IMAGE:figures/full_fig_p010_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Intent reasoning process for netlist synthesis, which demonstrates how intent reasoning extracts the correct components from three [PITH_FULL_IMAGE:figures/full_fig_p011_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Illustration of context compression using an LLM. The diagram shows how raw context is summarized into a compressed context, [PITH_FULL_IMAGE:figures/full_fig_p012_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Comparison before and after context truncation. This diagram demonstrates the process of removing redundant historical tool messages [PITH_FULL_IMAGE:figures/full_fig_p014_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Comparison of circuit element detection in di [PITH_FULL_IMAGE:figures/full_fig_p015_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Full execution example of the proposed AnalogMaster framework. (a) Original circuit image. (b) Annotated circuit image with identified [PITH_FULL_IMAGE:figures/full_fig_p018_10.png] view at source ↗
read the original abstract

Design automation has the potential to substantially improve the efficiency of analog integrated circuit (IC) design. However, existing algorithms and tools typically focus on individual stages, such as device sizing, placement, or routing, and still require significant manual intervention to complete the full design flow. While large language models (LLMs) have recently demonstrated remarkable success in automating digital IC design workflows, these advances cannot be directly transferred to analog IC design. Key challenges include strongly coupled performance metrics, the predominance of unstructured circuit schematic images, and the fact that most prior approaches address only isolated stages of the analog design process, limiting their ability to capture end-to-end performance impact. To address these challenges, we propose AnalogMaster, an extensible, LLM-based framework that enables end-to-end automation of analog IC design through a unified pipeline spanning circuit image-to-netlist generation, parameter optimization, placement, and routing. AnalogMaster integrates a joint reasoning mechanism that leverages in-context learning and intent reasoning to achieve accurate and robust image-to-netlist conversion. A parameter search agent integrating self-enhanced prompt engineering and context truncation is developed for effective device sizing and downstream physical design. Experimental evaluations on 15 representative circuits with varying levels of complexity demonstrate strong and consistent performance across multiple models. In particular, GPT-5 achieves success rates of 92.9% and 99.9% on Pass@1 and Pass@5, respectively. These results validate the effectiveness and robustness of the proposed framework and establish a practical paradigm for applying LLMs to full-stack analog IC design automation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The paper introduces AnalogMaster, an LLM-based framework for end-to-end analog IC design automation from unstructured schematic images through netlist generation, device sizing via parameter search, placement, and routing. It employs joint reasoning with in-context learning for image-to-netlist conversion and a self-enhanced prompt engineering agent with context truncation for parameter optimization. Experimental results on 15 representative circuits report GPT-5 achieving 92.9% Pass@1 and 99.9% Pass@5 success rates, claiming this validates a practical paradigm for full-stack analog design automation.

Significance. If the high success rates are shown to reflect verified satisfaction of coupled analog specifications (gain, bandwidth, stability, etc.) after layout extraction, the work would mark a notable advance in applying LLMs to analog design, a domain where traditional tools remain stage-specific and labor-intensive. The unified pipeline and handling of image inputs address real gaps in prior automation efforts. The empirical framing on external test circuits is a strength, but the absence of detailed verification protocols and baselines currently limits the assessed significance to a promising but preliminary demonstration.

major comments (3)
  1. [Abstract] Abstract: The central claim of 92.9% Pass@1 / 99.9% Pass@5 success rates for the parameter search agent is not accompanied by an explicit definition of success. It is unclear whether success requires closed-loop SPICE verification that the sized netlist meets target coupled performance metrics (including post-layout parasitics) or is limited to syntactic netlist validity or manual review.
  2. [Experimental evaluations] Experimental evaluations section: No baseline comparisons are provided against existing analog sizing tools (e.g., genetic algorithms, Bayesian optimization, or commercial analog design assistants), nor is there error analysis, failure-mode breakdown, or ablation of the self-enhanced prompting and context truncation components. This undermines assessment of whether the reported rates represent a genuine advance.
  3. [Pipeline description] Pipeline description (image-to-netlist and parameter optimization stages): The joint reasoning mechanism is asserted to handle strongly coupled metrics and unstructured images, yet no concrete examples, prompt templates, or quantitative metrics (e.g., netlist accuracy against ground-truth schematics) are supplied to substantiate robustness without substantial manual correction.
minor comments (2)
  1. [Abstract] The manuscript refers to 'GPT-5' without clarifying whether this denotes a publicly available model, a fine-tuned variant, or a hypothetical future system; this affects reproducibility.
  2. Figure captions and pipeline diagrams would benefit from explicit labeling of data flow between agents and any manual intervention points.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive and detailed feedback. The comments highlight important areas for improving clarity, rigor, and completeness. We address each major comment below and will revise the manuscript to incorporate the suggested changes where feasible.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central claim of 92.9% Pass@1 / 99.9% Pass@5 success rates for the parameter search agent is not accompanied by an explicit definition of success. It is unclear whether success requires closed-loop SPICE verification that the sized netlist meets target coupled performance metrics (including post-layout parasitics) or is limited to syntactic netlist validity or manual review.

    Authors: We agree that an explicit definition of success is essential for interpreting the reported rates. In our framework, success is determined by closed-loop SPICE verification: after parameter optimization, the sized netlist must satisfy the target coupled analog specifications (gain, bandwidth, stability margins, etc.). For circuits where the full pipeline is executed, this includes post-layout parasitic extraction. The Pass@k metric counts a trial as successful only if the verified performance meets all targets within tolerance. We will revise the abstract and add a dedicated subsection in the experimental evaluations to state this definition clearly, including the verification protocol. revision: yes

  2. Referee: [Experimental evaluations] Experimental evaluations section: No baseline comparisons are provided against existing analog sizing tools (e.g., genetic algorithms, Bayesian optimization, or commercial analog design assistants), nor is there error analysis, failure-mode breakdown, or ablation of the self-enhanced prompting and context truncation components. This undermines assessment of whether the reported rates represent a genuine advance.

    Authors: We acknowledge the value of baselines and component ablations for contextualizing the results. Our experiments emphasize the end-to-end LLM pipeline on image inputs, which existing tools do not support directly. In the revision we will add: (1) an ablation study isolating the contributions of self-enhanced prompt engineering and context truncation, (2) error analysis and failure-mode categorization across the 15 circuits, and (3) direct comparisons against genetic algorithms and Bayesian optimization on the same netlist-level sizing tasks (noting that image-to-netlist conversion remains LLM-specific). Full commercial-tool comparisons are resource-intensive but will be discussed qualitatively with references to prior analog sizing literature. revision: partial

  3. Referee: [Pipeline description] Pipeline description (image-to-netlist and parameter optimization stages): The joint reasoning mechanism is asserted to handle strongly coupled metrics and unstructured images, yet no concrete examples, prompt templates, or quantitative metrics (e.g., netlist accuracy against ground-truth schematics) are supplied to substantiate robustness without substantial manual correction.

    Authors: We will strengthen the pipeline section by including: representative examples of unstructured schematic images and the corresponding generated netlists, the exact prompt templates for joint reasoning and in-context learning, and quantitative metrics (component detection accuracy, net connectivity precision, and overall netlist fidelity) measured against ground-truth schematics for all 15 test circuits. These additions will be placed in the main text or a new appendix to demonstrate that the joint reasoning operates with minimal manual correction. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical framework with external circuit evaluations

full rationale

The paper describes an applied LLM-based pipeline for analog IC design (image-to-netlist, sizing, placement, routing) and reports empirical success rates on 15 independent test circuits. No equations, derivations, fitted parameters renamed as predictions, or self-definitional steps exist. Claims rest on experimental outcomes rather than any chain that reduces to its own inputs by construction. No load-bearing self-citations or uniqueness theorems are invoked; the work is self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on unproven assumptions about LLM reasoning capabilities for circuit diagrams and the effectiveness of custom prompt engineering for analog constraints; no free parameters or new entities are explicitly introduced.

axioms (2)
  • domain assumption Large language models can accurately convert unstructured circuit schematic images to netlists using in-context learning and intent reasoning
    Core mechanism for the first stage of the pipeline.
  • ad hoc to paper Self-enhanced prompt engineering combined with context truncation enables effective device sizing that respects coupled performance metrics
    Basis for the parameter optimization agent.

pith-pipeline@v0.9.0 · 5589 in / 1438 out tokens · 40546 ms · 2026-05-09T23:52:59.265121+00:00 · methodology

discussion (0)

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