PCB-QA is the first QA benchmark for LLMs on printed circuit board designs, with Gemini 3 Flash Preview reaching 93% accuracy on a JSON textual representation.
AutoChip: Automating hdl generation using llm feedback
13 Pith papers cite this work, alongside 17 external citations. Polarity classification is still indexing.
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Pith papers citing it
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2026 13representative citing papers
RTL-BenchLS supplies a large-scale formally verified benchmark and three novel tasks that expose low performance of frontier LLMs on realistic RTL reasoning and generation.
An LLM agent iteratively applies a sound hardware refinement calculus to turn design specs into correct-by-construction RTL, reaching 92.3% pass@1 on VerilogEval.
ChipCraftBrain achieves 97.2% pass rate on VerilogEval and 94.7% on CVDP benchmarks for generating functional RTL code using adaptive multi-agent orchestration and hybrid reasoning.
SINA converts circuit schematic images to netlists at 96.67% accuracy using deep learning, OCR, connected-component labeling, and a vision-language model, claimed 2.72x better than prior methods.
AnalogMaster applies large language models to end-to-end analog IC design automation, converting images to netlists and optimizing parameters to achieve 92.9% Pass@1 and 99.9% Pass@5 success on 15 test circuits using GPT-5.
IR choice dominates model choice in LLM hardware generation from natural language, with simulation pass rates ranging 3-88% across IRs but varying less than 1.25x across models.
VeriPilot raises GPT-4o Verilog repair success from 54.3% to 85.71% on the CVDP benchmark by using golden-model semantic alignment and CDFG-based signal tracing.
ROSUM-MCTS applies MCTS-inspired hierarchical candidate expansion and a composite reward balancing functional correctness, local content adequacy, and fluency to improve LLM summaries of VHDL and Verilog code, outperforming baselines on eval datasets.
LEGO extracts 42 standardized circuit skills from 11 open-source projects into a plug-and-play platform that raises Pass@1 from 0 to 0.805 on 41 hard VerilogEval v2 problems.
VerilogCL applies contrastive learning with minimal-error data pairs and a proactive screening module to improve compilation success and functional correctness of 7B LLM-generated Verilog over open-source and commercial baselines on VerilogEval and RTLLM benchmarks.
HORIZON applies repository-level self-evolution to hardware design artifacts and reports 100% completion on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories using a hands-free agent loop.
Survey of GenAI in PCB design lifecycle presenting taxonomy, technical challenges, and research directions.
citing papers explorer
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PCB-QA: Evaluating LLMs over the First Printed Circuit Board Design Question-Answer Dataset
PCB-QA is the first QA benchmark for LLMs on printed circuit board designs, with Gemini 3 Flash Preview reaching 93% accuracy on a JSON textual representation.
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RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
RTL-BenchLS supplies a large-scale formally verified benchmark and three novel tasks that expose low performance of frontier LLMs on realistic RTL reasoning and generation.
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Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
An LLM agent iteratively applies a sound hardware refinement calculus to turn design specs into correct-by-construction RTL, reaching 92.3% pass@1 on VerilogEval.
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ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
ChipCraftBrain achieves 97.2% pass rate on VerilogEval and 94.7% on CVDP benchmarks for generating functional RTL code using adaptive multi-agent orchestration and hybrid reasoning.
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SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence
SINA converts circuit schematic images to netlists at 96.67% accuracy using deep learning, OCR, connected-component labeling, and a vision-language model, claimed 2.72x better than prior methods.
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AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout
AnalogMaster applies large language models to end-to-end analog IC design automation, converting images to netlists and optimizing parameters to achieve 92.9% Pass@1 and 99.9% Pass@5 success on 15 test circuits using GPT-5.
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From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
IR choice dominates model choice in LLM hardware generation from natural language, with simulation pass rates ranging 3-88% across IRs but varying less than 1.25x across models.
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VeriPilot: An LLM-Powered Verilog Debugging Framework
VeriPilot raises GPT-4o Verilog repair success from 54.3% to 85.71% on the CVDP benchmark by using golden-model semantic alignment and CDFG-based signal tracing.
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ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards
ROSUM-MCTS applies MCTS-inspired hierarchical candidate expansion and a composite reward balancing functional correctness, local content adequacy, and fluency to improve LLM summaries of VHDL and Verilog code, outperforming baselines on eval datasets.
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LEGO: An LLM Skill-Based Front-End Design Generation Platform
LEGO extracts 42 standardized circuit skills from 11 open-source projects into a plug-and-play platform that raises Pass@1 from 0 to 0.805 on 41 hard VerilogEval v2 problems.
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VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
VerilogCL applies contrastive learning with minimal-error data pairs and a proactive screening module to improve compilation success and functional correctness of 7B LLM-generated Verilog over open-source and commercial baselines on VerilogEval and RTLLM benchmarks.
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Agentic Hardware Design as Repository-Level Code Evolution
HORIZON applies repository-level self-evolution to hardware design artifacts and reports 100% completion on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories using a hands-free agent loop.
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Surveying GenAI-based Automation in Printed Circuit Board Design and Test
Survey of GenAI in PCB design lifecycle presenting taxonomy, technical challenges, and research directions.