pith. sign in

arxiv: 2605.00032 · v1 · submitted 2026-04-24 · 💻 cs.AR · cs.LG

ROSA: Robust and Energy-Efficient Microring-Based Optical Neural Networks via Optical Shift-and-Add and Layer-Wise Hybrid Mapping

Huifan Zhang , Yun Hu , Caizhi Sheng , Yurui Qu , Pingqiang Zhou This is my paper

Pith reviewed 2026-05-09 20:07 UTC · model grok-4.3

classification 💻 cs.AR cs.LG
keywords optical neural networksmicroring resonatorsenergy efficiencyrobustnesshybrid mappingshift-and-addCIFAR-10
0
0 comments X

The pith

ROSA architecture improves microring optical neural networks with optical shift-and-add and layer-wise hybrid mapping for better robustness and efficiency.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces ROSA, an architecture for microring-based optical neural networks that adds an optical shift-and-add module to perform computations with lower energy cost and a layer-wise hybrid mapping strategy to balance data movement across layers. It includes a noise-aware voltage-to-weight model that incorporates DAC and thermal variations to improve reliability in hardware. Workload-aware optimization of array size and dataflow leads to lower energy-delay products in simulations while maintaining or improving accuracy on standard tasks.

Core claim

ROSA integrates an optical shift-and-add module and a hybrid mapping approach in microring arrays to achieve 64% lower aggregated relative energy-delay product than DEAP-CNNs and 26% lower than a general compact array, with OSA adding a further 29% EDP reduction; the hybrid strategy also raises CIFAR-10 accuracy by 8.3% over weight-stationary mapping at 54.7% lower average EDP.

What carries the argument

The optical shift-and-add (OSA) module that performs optical signal shifting and addition, paired with a workload-aware co-optimization framework for microring array sizing and per-layer dataflow mapping.

Load-bearing premise

The noise-aware voltage-to-weight model correctly captures DAC and thermal variations, so that simulated EDP and accuracy gains will appear in actual fabricated microring hardware without large unmodeled effects.

What would settle it

Build a physical ROSA prototype on microring hardware, run it on CIFAR-10, and compare measured energy-delay product and accuracy against the paper's simulation numbers.

Figures

Figures reproduced from arXiv: 2605.00032 by Caizhi Sheng, Huifan Zhang, Pingqiang Zhou, Yun Hu, Yurui Qu.

Figure 1
Figure 1. Figure 1: Previous and proposed MRR-ONN dataflow. on slow TO tuning for analog weight updates or sacrifice high throughput using digital EO encoding. Additionally, the nature of photons makes it difficult to store and buffer the outputs. In prior MRR-ONN architec￾tures, there is a lack of output reuse mechanisms, as illus￾trated in [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Architecture of the proposed MRR-based ONN accelerator with optical shift-and-add module. c × = (a) Input Trough λ1 λ2 λ3 λ4 V oltage TI A Photo Diode (b) MRR Ni-bit Quantization Nw-bit Quantization No -bit Quantization No -bit Quantization Ti me-D o main Encoding 3 2 1 0 × = × = × × = = Wavelength-Domain Multiplexing (c) 1-bit Quantization Nw-bit Quantization No -bit Quantization 1/8 1/4 1/2 1/1 T=0 T=1 T… view at source ↗
Figure 3
Figure 3. Figure 3: MAC computing paradigms using integrated MRRs and optical shift-and-add module. (a) Conventional broadcast-and-weight mode. (b) The basic MRR MAC unit. (c) Proposed optical shift-and-add module. This OSA module naturally supports digital-analog MAC operations. Assume a normalized input 𝑥𝑘 ∈ (−1, 1) is quan￾tized into 𝑁𝑇 bits using balanced ternary symbols 𝑏𝑘,𝑡 ∈ {0, −1, 1}, where 𝑏𝑘,0 and 𝑏𝑘,𝑇 denote the l… view at source ↗
Figure 4
Figure 4. Figure 4: Different mapping strategies for MRR-ONN. Convolution mapping. Previous works on MRR-ONN usu￾ally use weight-stationary scheme for full convolution layers: the bias voltages on the weight MRRs are held constant while the inner loops iterate over input features ( [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: (a) MRR transmission characteristics around 𝜆0 = 1538.739 nm. (b) Voltage tuning from 1V to 3V, max wave￾length shift: 0.740 nm. (c) Experimental vs theoretical corre￾lation. their respective stages, i.e., 𝜀DAC ∼ N (0, 𝜎2 DAC) and 𝜀th ∼ N (0, 𝜎2 th). 𝑉 ′ = 𝑉 + 𝜀DAC, Δ𝑇 ′ (𝑉 ′ ) = 𝑉 ′2 𝑅ℎ 𝑅th + 𝜀𝑇 . (8) The above noise analysis stands for TO-tuned MRRs. For the EO-tuned MRRs which operate via the free-carri… view at source ↗
Figure 6
Figure 6. Figure 6: Layer-wise accuracy and EDP comparison between input-stationary and weight-stationary mapping. and normalize each candidate by its per-layer best: 𝑑 ref 𝑙 = min{𝑑𝑙 (IS), 𝑑𝑙 (WS)}, 𝑒ref 𝑙 = min{𝑒𝑙 (IS), 𝑒𝑙 (WS)}, The balanced metric for each mapping is arg min 𝑚 𝑀𝑙 (𝑚) =  𝑑𝑙 (𝑚) 𝑑 ref 𝑙 𝛼𝑙  𝑒𝑙 (𝑚) 𝑒 ref 𝑙 1−𝛼𝑙 , 𝑚 ∈ {IS, WS}. where the accuracy weight 𝛼𝑙 ∈ [0, 1] is layer-adaptive: 𝛼𝑙 = 𝛼min +𝛾 log 1 +… view at source ↗
Figure 7
Figure 7. Figure 7: Energy–Delay Product (EDP) Scaling Across Neu￾ral Network Architectures shifts with optical accumulation, thereby substantially re￾ducing the energy of optical-analog and analog-digital con￾version. As shown in [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: EDP reduction with optical shift-and-add [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: Accuracy and loss comparison of different map￾ping methods under thermal and DAC noise. 5 Conclusion This paper demonstrates that combining optical shift-and￾add with time-wavelength digital-analog MACs and noise￾aware mapping significantly improves both efficiency and robustness of MRR-based ONNs. Across CNNs and Trans￾formers, optimized arrays and OSA jointly reduce EDP while a hybrid mapping strategy m… view at source ↗
read the original abstract

This work presents ROSA, a microring-based optical neural network architecture that improves robustness and energy efficiency using an optical shift-and-add (OSA) module and a layer-wise hybrid mapping strategy. It introduces a noise-aware voltage-to-weight model considering DAC and thermal variations, and a workload-aware framework to co-optimize MRR array size and layer-wise dataflow. Optimized arrays reduce the aggregated relative energy-delay product (EDP) by 64% and 26% compared with DEAP-CNNs and a general compact array, respectively. OSA further contributes 29% EDP reduction. The proposed hybrid mapping strategy improves CIFAR-10 accuracy by 8.3% over weight-stationary mapping while achieving an average 54.7% lower EDP than DEAP-CNNs.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. This paper presents ROSA, a microring-based optical neural network architecture that uses an optical shift-and-add (OSA) module and a layer-wise hybrid mapping strategy to improve robustness and energy efficiency. It develops a noise-aware voltage-to-weight model incorporating DAC and thermal variations, together with a workload-aware co-optimization framework for MRR array size and dataflow. Simulation results claim 64% and 26% reductions in aggregated relative EDP versus DEAP-CNNs and general compact arrays respectively, an additional 29% EDP reduction from OSA, and an 8.3% CIFAR-10 accuracy improvement over weight-stationary mapping with 54.7% lower average EDP.

Significance. If the simulation results hold under realistic hardware conditions, the OSA module and hybrid mapping approach could meaningfully advance energy-efficient and robust photonic neural network accelerators by mitigating key noise and mapping challenges in microring arrays. The co-optimization framework and explicit noise model represent concrete contributions that could be adopted in future optical computing designs.

major comments (2)
  1. [Noise Model (methods) and Results (evaluation)] The headline quantitative claims (64% EDP reduction vs. DEAP-CNNs, 29% from OSA, 8.3% accuracy gain) rest entirely on the noise-aware voltage-to-weight model. This model accounts only for DAC and thermal variations; the manuscript contains no sensitivity analysis or bounding argument showing that omitted effects (inter-ring crosstalk, wavelength drift under load, fabrication resonance shifts) remain negligible at the reported operating points. Because the EDP and accuracy numbers are direct outputs of this model, the central performance claims cannot be assessed without additional validation or analysis of model completeness.
  2. [Evaluation and Results sections] All reported EDP and accuracy figures are obtained from simulation under the custom noise model with no error bars, no multiple random seeds, and no fabricated-chip measurements. The absence of hardware validation or cross-check against measured microring characteristics makes the 64%/26%/29% EDP reductions and 8.3% accuracy delta load-bearing only under the untested assumption that the model captures all dominant error sources.
minor comments (2)
  1. [Figures in Results] Figure captions and axis labels for EDP and accuracy plots should explicitly state that all values are simulation-derived under the DAC+thermal noise model.
  2. [Abstract and §1] The abstract and introduction should clarify early that all quantitative results are simulation-based rather than measured on silicon.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the thorough and constructive review of our manuscript on ROSA. We address each major comment point by point below, with planned revisions noted where appropriate.

read point-by-point responses

  1. Referee: [Noise Model (methods) and Results (evaluation)] The headline quantitative claims (64% EDP reduction vs. DEAP-CNNs, 29% from OSA, 8.3% accuracy gain) rest entirely on the noise-aware voltage-to-weight model. This model accounts only for DAC and thermal variations; the manuscript contains no sensitivity analysis or bounding argument showing that omitted effects (inter-ring crosstalk, wavelength drift under load, fabrication resonance shifts) remain negligible at the reported operating points. Because the EDP and accuracy numbers are direct outputs of this model, the central performance claims cannot be assessed without additional validation or analysis of model completeness.

    Authors: We appreciate the referee's emphasis on model completeness. Our noise-aware voltage-to-weight model prioritizes DAC quantization and thermal variations because these are the dominant, controllable error sources in the targeted low-power microring operating regime, consistent with prior device modeling literature. We agree that explicit sensitivity analysis would strengthen the claims. In the revised manuscript we will add a new subsection with bounding arguments and sensitivity plots for inter-ring crosstalk, wavelength drift under load, and fabrication resonance shifts, using parameters drawn from recent experimental reports. These additions will show that the omitted effects remain secondary at the simulated operating points and do not overturn the reported EDP and accuracy gains. revision: yes

  2. Referee: [Evaluation and Results sections] All reported EDP and accuracy figures are obtained from simulation under the custom noise model with no error bars, no multiple random seeds, and no fabricated-chip measurements. The absence of hardware validation or cross-check against measured microring characteristics makes the 64%/26%/29% EDP reductions and 8.3% accuracy delta load-bearing only under the untested assumption that the model captures all dominant error sources.

    Authors: We acknowledge that all quantitative results are simulation-based and that hardware validation is absent. This is a recognized limitation of architectural studies in emerging photonic technologies. To improve statistical rigor, the revised evaluation will include error bars obtained from multiple independent simulation runs with randomized noise seeds. We will also add a direct comparison of our model parameters against published measured microring resonator characteristics to provide cross-validation. While new chip fabrication lies outside the scope and resources of the current work, we will explicitly discuss the simulation-only nature and its assumptions as a limitation in the revised manuscript. revision: partial

standing simulated objections not resolved
  • Direct fabricated-chip measurements and hardware validation, which cannot be supplied because the study is simulation-based and no physical prototypes were available.

Circularity Check

0 steps flagged

No significant circularity detected

full rationale

The paper introduces an explicit new architecture (ROSA) with OSA module and layer-wise hybrid mapping, plus a newly defined noise-aware voltage-to-weight model that incorporates DAC and thermal effects. All quantitative claims (64% and 26% EDP reductions vs. DEAP-CNNs and compact array, 29% further EDP reduction from OSA, 8.3% CIFAR-10 accuracy gain over weight-stationary mapping) are computed from simulations under this model and compared against external published baselines or internal mapping variants. No derivation step reduces by construction to its own inputs, no fitted parameter is relabeled as a prediction, and no load-bearing premise rests on a self-citation chain. The workload-aware co-optimization produces the reported array sizes and mappings as outputs rather than presupposing the final metrics.

Axiom & Free-Parameter Ledger

2 free parameters · 1 axioms · 0 invented entities

Only the abstract is available, so the ledger is inferred from the described components; the paper likely relies on several modeling assumptions and optimization parameters whose exact values and independence are not stated.

free parameters (2)
  • MRR array size
    Co-optimized per workload in the framework; chosen to minimize EDP rather than derived from first principles.
  • Layer-wise mapping parameters
    Hybrid mapping decisions tuned for each layer to trade accuracy against energy.
axioms (1)
  • domain assumption The custom noise-aware voltage-to-weight model sufficiently captures real DAC quantization and thermal drift effects.
    Invoked to justify robustness claims and EDP calculations.

pith-pipeline@v0.9.0 · 5453 in / 1389 out tokens · 50769 ms · 2026-05-09T20:07:02.692893+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

31 extracted references · 31 canonical work pages

  1. [1]

    An integrated large-scale photonic accelerator with ultralow latency.Nature, 640(8058):361–367, 2025

    Shiyue Hua, Erwan Divita, Shanshan Yu, Bo Peng, Charles Roques- Carmes, Zhan Su, Zhang Chen, Yanfei Bai, Jinghui Zou, Yunpeng Zhu, et al. An integrated large-scale photonic accelerator with ultralow latency.Nature, 640(8058):361–367, 2025

    work page 2025

  2. [2]

    Universal photonic artificial intelligence acceleration

    Sufi R Ahmed, Reza Baghdadi, Mikhail Bernadskiy, Nate Bowman, Ryan Braid, Jim Carr, Chen Chen, Pietro Ciccarella, Matthew Cole, John Cooke, et al. Universal photonic artificial intelligence acceleration. Nature, 640(8058):368–374, 2025

    work page 2025

  3. [3]

    Toward intelligent electronic-photonic design automation for large-scale photonic inte- grated circuits: from device inverse design to physical layout genera- tion

    Hongjian Zhou, Pingchuan Ma, and Jiaqi Gu. Toward intelligent electronic-photonic design automation for large-scale photonic inte- grated circuits: from device inverse design to physical layout genera- tion. InOptical Design Automation, volume 13601, pages 69–78. SPIE, 2025

    work page 2025

  4. [4]

    Fiona: Photonic-electronic cosimulation framework and transferable prototyping for photonic accelerator

    Yinyi Liu, Bohan Hu, Zhenguo Liu, Peiyu Chen, Linfeng Du, Jiaqi Liu, Xianbin Li, Wei Zhang, and Jiang Xu. Fiona: Photonic-electronic cosimulation framework and transferable prototyping for photonic accelerator. InIEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 1–9. IEEE, 2023

    work page 2023

  5. [5]

    Zhu, Jun Zou, Hengyi Zhang, Y.Z

    H.H. Zhu, Jun Zou, Hengyi Zhang, Y.Z. Shi, S.B. Luo, N. Wang, H. Cai, L.X. Wan, Bo Wang, X.D. Jiang, et al. Space-efficient optical com- puting with an integrated chip diffractive neural network.Nature communications, 13(1):1044, 2022

    work page 2022

  6. [6]

    Toward lifelong-sustainable electronic- photonic ai systems via extreme efficiency, reconfigurability, and ro- bustness.arXiv preprint arXiv:2509.07396, 2025

    Ziang Yin, Hongjian Zhou, Chetan Choppali Sudarshan, Vidya Chhabria, and Jiaqi Gu. Toward lifelong-sustainable electronic- photonic ai systems via extreme efficiency, reconfigurability, and ro- bustness.arXiv preprint arXiv:2509.07396, 2025

    work page arXiv 2025

  7. [7]

    Neuromor- phic photonic networks using silicon photonic weight banks.Scientific reports, 7(1):7430, 2017

    Alexander N Tait, Thomas Ferreira De Lima, Ellen Zhou, Allie X Wu, Mitchell A Nahmias, Bhavin J Shastri, and Paul R Prucnal. Neuromor- phic photonic networks using silicon photonic weight banks.Scientific reports, 7(1):7430, 2017

    work page 2017

  8. [8]

    Broadcast and weight: an integrated network for scalable pho- tonic spike processing.Journal of Lightwave Technology, 32(21):3427– 3439, 2014

    Alexander N Tait, Mitchell A Nahmias, Bhavin J Shastri, and Paul R Prucnal. Broadcast and weight: an integrated network for scalable pho- tonic spike processing.Journal of Lightwave Technology, 32(21):3427– 3439, 2014

    work page 2014

  9. [9]

    Digital electronics and analog photonics for convolutional neural networks (deap-cnns).IEEE journal of selected topics in quantum electronics, 26(1):1–13, 2019

    Viraj Bangari, Bicky A Marquez, Heidi Miller, Alexander N Tait, Mitchell A Nahmias, Thomas Ferreira De Lima, Hsuan-Tung Peng, Paul R Prucnal, and Bhavin J Shastri. Digital electronics and analog photonics for convolutional neural networks (deap-cnns).IEEE journal of selected topics in quantum electronics, 26(1):1–13, 2019

    work page 2019

  10. [10]

    Holylight: A nanophotonic accelerator for deep learning in data centers

    Weichen Liu, Wenyang Liu, Yichen Ye, Qian Lou, Yiyuan Xie, and Lei Jiang. Holylight: A nanophotonic accelerator for deep learning in data centers. InDesign, Automation & Test in Europe Conference (DATE), pages 1483–1488. IEEE, 2019

    work page 2019

  11. [11]

    Crosslight: A cross-layer optimized silicon photonic neural network accelerator

    Febin Sunny, Asif Mirza, Mahdi Nikdast, and Sudeep Pasricha. Crosslight: A cross-layer optimized silicon photonic neural network accelerator. InACM/IEEE design automation conference (DAC), pages 1069–1074. IEEE, 2021

    work page 2021

  12. [12]

    Squeezelight: a multi- operand ring-based optical neural network with cross-layer scalability

    Jiaqi Gu, Chenghao Feng, Hanqing Zhu, Zheng Zhao, Zhoufeng Ying, Mingjie Liu, Ray T Chen, and David Z Pan. Squeezelight: a multi- operand ring-based optical neural network with cross-layer scalability. Transactions on Computer-Aided Design of Integrated Circuits and Sys- tems, 42(3):807–819, 2022

    work page 2022

  13. [13]

    Lightening-transformer: A dynamically-operated optically- interconnected photonic transformer accelerator

    Hanqing Zhu, Jiaqi Gu, Hanrui Wang, Zixuan Jiang, Zhekai Zhang, Rongxing Tang, Chenghao Feng, Song Han, Ray T Chen, and David Z Pan. Lightening-transformer: A dynamically-operated optically- interconnected photonic transformer accelerator. InIEEE International Symposium on High-Performance Computer Architecture (HPCA), pages 686–703. IEEE, 2024

    work page 2024

  14. [14]

    Thermo-optic phase shifters based on silicon-on-insulator platform: state-of-the-art and a review.Frontiers of Optoelectronics, 15(1):9, 2022

    Shengping Liu, Junbo Feng, Ye Tian, Heng Zhao, Li Jin, Boling Ouyang, Jiguang Zhu, and Jin Guo. Thermo-optic phase shifters based on silicon-on-insulator platform: state-of-the-art and a review.Frontiers of Optoelectronics, 15(1):9, 2022

    work page 2022

  15. [15]

    A 5 × 200 gbps microring modulator silicon chip empowered by two-segment z-shape junctions.Nature Communications, 15(1):918, 2024

    Yuan Yuan, Yiwei Peng, Wayne V Sorin, Stanley Cheung, Zhihong Huang, Di Liang, Marco Fiorentino, and Raymond G Beausoleil. A 5 × 200 gbps microring modulator silicon chip empowered by two-segment z-shape junctions.Nature Communications, 15(1):918, 2024

    work page 2024

  16. [16]

    Scalable in-memory compute optical processor

    Sugeet Sunder, Md Abdullah-Al Kaiser, Sasindu Wijeratne, Clynn J Mathew, Viktor Prasanna, Akhilesh Jaiswal, and Ajey Jacob. Scalable in-memory compute optical processor. InSmart Photonic and Opto- electronic Integrated Circuits 2025, volume 13370, pages 107–113. SPIE, 2025

    work page 2025

  17. [17]

    Fast thermal switching of wideband optical delay line with no long- term transient.IEEE Photonics Technology Letters, 24(6):512–514, 2011

    Paul A Morton, Jaime Cardenas, Jacob B Khurgin, and Michal Lipson. Fast thermal switching of wideband optical delay line with no long- term transient.IEEE Photonics Technology Letters, 24(6):512–514, 2011

    work page 2011

  18. [18]

    Network of time-multiplexed optical parametric oscillators as a coherent ising machine.Nature Photonics, 8(12):937–942, 2014

    Alireza Marandi, Zhe Wang, Kenta Takata, Robert L Byer, and Yoshihisa Yamamoto. Network of time-multiplexed optical parametric oscillators as a coherent ising machine.Nature Photonics, 8(12):937–942, 2014

    work page 2014

  19. [19]

    Single-monitor calibration for multiple microring synapses

    Xinyu Liu, Wenkai Zhang, Junwei Cheng, Hailong Zhou, and Jianji Dong. Single-monitor calibration for multiple microring synapses. ACS Photonics, 11(7):2570–2577, 2024

    work page 2024

  20. [20]

    Quantifying power in silicon photonic neural net- works.Physical Review Applied, 17(5):054029, 2022

    Alexander N Tait. Quantifying power in silicon photonic neural net- works.Physical Review Applied, 17(5):054029, 2022

    work page 2022

  21. [21]

    Heterogeneously integrated iii-v/si distributed bragg reflector laser with adiabatic coupling

    A Descos, C Jany, D Bordel, H Duprez, G Beninca de Farias, P Bri- anceau, S Menezo, and B Ben Bakir. Heterogeneously integrated iii-v/si distributed bragg reflector laser with adiabatic coupling. InEuropean Conference on Optical Communication (ECOC), pages 687–689. IET, 2013

    work page 2013

  22. [22]

    8-bit 5gs/s d/a converter for multi-gigabit wireless transceivers

    Behnam Sedighi, Mahdi Khafaji, and J Christoph Scheytt. 8-bit 5gs/s d/a converter for multi-gigabit wireless transceivers. InEuropean Microwave Integrated Circuit Conference, pages 192–195. IEEE, 2011

    work page 2011

  23. [23]

    Single-chip microprocessor that communicates directly using light.Nature, 528(7583):534–538, 2015

    Chen Sun, Mark T Wade, Yunsup Lee, Jason S Orcutt, Luca Alloatti, Michael S Georgas, Andrew S Waterman, Jeffrey M Shainline, Rimas R Avizienis, Sen Lin, et al. Single-chip microprocessor that communicates directly using light.Nature, 528(7583):534–538, 2015

    work page 2015

  24. [24]

    A 128kb high density portless sram using hi- erarchical bitlines and thyristor sense amplifiers

    Michael Wieckowski, Gregory K Chen, Daeyeon Kim, David Blaauw, and Dennis Sylvester. A 128kb high density portless sram using hi- erarchical bitlines and thyristor sense amplifiers. InInternational Symposium on Quality Electronic Design, pages 1–4. IEEE, 2011

    work page 2011

  25. [25]

    Modeling analog-digital-converter energy and area for compute-in-memory accelerator design.arXiv preprint arXiv:2404.06553, 2024

    Tanner Andrulis, Ruicong Chen, Hae-Seung Lee, Joel S Emer, and Vivienne Sze. Modeling analog-digital-converter energy and area for compute-in-memory accelerator design.arXiv preprint arXiv:2404.06553, 2024

    work page arXiv 2024

  26. [26]

    O-has: Optical hardware accelerator search for boosting both acceleration performance and development speed

    Mengquan Li, Zhongzhi Yu, Yongan Zhang, Yonggan Fu, and Yingyan Lin. O-has: Optical hardware accelerator search for boosting both acceleration performance and development speed. InIEEE/ACM Inter- national Conference On Computer Aided Design (ICCAD), pages 1–9. IEEE, 2021

    work page 2021

  27. [27]

    In-situ trained microring- based neural networks for scalable and robust photonic computing

    Baiheng Zhao, Bo Wu, Shangsen Sun, Shiji Zhang, Dingshan Gao, Hai- long Zhou, Jianji Dong, and Xinliang Zhang. In-situ trained microring- based neural networks for scalable and robust photonic computing. Laser & Photonics Reviews, page e01576, 2025

    work page 2025

  28. [28]

    Quantized optical neural network based on microring resonators with on-chip modulation

    Yun Hu, Huifan Zhang, and Pingqiang Zhou. Quantized optical neural network based on microring resonators with on-chip modulation. In IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pages 674–678. IEEE, 2024

    work page 2024

  29. [29]

    Timeloop: A systematic approach to dnn accelerator evaluation

    Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W Keckler, and Joel Emer. Timeloop: A systematic approach to dnn accelerator evaluation. InIEEE Interna- tional Symposium on Performance Analysis of Systems and Software (ISPASS), pages 304–315. IEEE, 2019

    work page 2019

  30. [30]

    Cimloop: A flexible, accurate, and fast compute-in-memory modeling tool

    Tanner Andrulis, Joel S Emer, and Vivienne Sze. Cimloop: A flexible, accurate, and fast compute-in-memory modeling tool. InIEEE Inter- national Symposium on Performance Analysis of Systems and Software (ISPASS), pages 10–23. IEEE, 2024

    work page 2024

  31. [31]

    Architecture-level modeling of photonic deep neural network accelerators

    Tanner Andrulis, Gohar Irfan Chaudhry, Vinith M Suriyakumar, Joel S Emer, and Vivienne Sze. Architecture-level modeling of photonic deep neural network accelerators. InIEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 307–309. IEEE, 2024

    work page 2024